IP Core

RISC-V IP CORE FIE310G(RV32G)

FIE310G is a high performance, low power embedded real time RISC-V processor IPCore.

The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Features:

  1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
  2. 3-stage pipeline architecture
  3. support machine mode only
  4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
  5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
  6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
  1. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
  2. 2 UART
  3. 3 QSPI
  4. I2C
  5. 3 PWM
  6. 10M/100M/1G ethernet
  7. Watchdog
  8. 32 GPIO
  9. 4 7-seg display interface
  10. External Serial Flash
  11. Debug Interfaces: JTAG
  12. 12-Bit ADC
  13. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
  14. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

The entire system is designed by the verilog language, and all IPs can be added, deleted and reconfigured.

Figure 1  ALU Unit
Figure 2 Decode Unit
Figure 3 software set timer
Figure 4 software interrupt setting

The FII-PRX100 RISC-V development board introduction

  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertor, QSPI flash, I2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO , hdmi transmitter and camera etc.

RISC-V IPCore user development Guide

Risc-V FPGA Board PRX100
Risc-V FPGA Board PRX100

This document is edited by Fraser Innovation Inc. Step by step introduce how to develop each RISC-V CPU RTL modules based on RISC-V ISA, Simulations and board verifications, software environment and details on C language development, debug and program

Fraser Innovation Inc. is a leading FPGA based system design and RF application solution company serving students, college, universities, and OEM’s worldwide with technology-based educational design tools. Based in Richmond, British Columbia, Canada, Fraser Innovation  designs, manufactures, and distributes its products on a worldwide basis. We are top wireless communication educational device provider.

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