Altera RISC-V SoC AI FPGA Development Board Educational Platform

Xilinx and Altera Risc-V FPGA Board

Risc-V FPGA Boards, Risc-V Learning Boards – Step by Step teaching you how to code in RISC-V machine

Risc-V Board One: FII-PRX100 Development Board ARTIX 100T, XC7A100T – Xinlix FPGA Board

Risc-V FPGA Board PRX100
Risc-V FPGA Board PRX100 – Xinlinx Risc-V FPGA Boards

FII-PRX100 RISC-V development board

  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertorQSPI flashI2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO hdmi transmitter and camera etc.

System Design Objective

The main purpose of this system design is to complete FPGA learning, development and experiment with Xilin-Vivado. The main device uses the Xilinx-XC7A100T-2FGG676I and is currently the latest generation of FPGA devices from Xilinx. The main learning and development projects can be completed as follows:

  1. Basic FPGA design training
  2. Construction and training of the SOPC (Microblaze) system
  3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
  4. Development and application based on RISC-V
  5. The system is specifically optimized for hardware design for RISC-V system applications

2. System Resource

  1. Extended memory
  2. Use two Super Srams in parallel to form a 32-bit data interface with a maximum access space of 2M bytes.
  3. IS61WV51216 (2 pieces) 512K x 32bit
  4. Serial flash
  5. Spi interface serial flash (128M bytes)
  6. Serial EEPROM
  7. Gigabit Ethernet: 100/1000 Mbps
  8. USB to serial interface: USB-UART bridge

 

3. Human-computer Interaction Interface

  1. 8 toggle switches
  2. 8 push buttons
  3. Definition of 7 push buttons: up, down, left, right, ok, menu, return
  4. 1 for rest: Reset button
  5. 8 LEDs
  6. 6 7-segment decoders
  7. I2C bus interface
  8. UART external interface
    1. Two JTAG programming interfaces
  9. One is for downloading the FPGA debug interface, and the other one is the JTAG debug interface for the RISC-V CPU
  10. Built-in RISC-V
  11. CPU software debugger, no external RISC-V JTAG emulator required
    1. 12-pin GIPIO connectors, in line with PMOD interface standards

 

Software Development System

  1. Vivado 18.1 and later version for FPGA development, Microblaze SOPC
  2. Freedom Studio-Win_x86_64 Software development for RISC-V CPU

5.  Supporting Resources

    1. RISC-V  JTAG Debugger
    2. xilinx Altera JTAG Download Debugger
    3. FII-PRX100 Development Guide

Click Here to Buy Xilinx Risc-V FPGA Board FII-PRX100

 

The Risc-V Learning Tutors for PRX100 Risc-V FPGA Boards:

 

Altera Risc-V Board Two: FII-PRA040 Altera risc-v SOPC AI Cyclone10

FII-PRA040 Risc-V Educational Platform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Intel Altera.

It was designed for use in all fields of FPGA development and experiments.

Communication

Digital Communication DSP(FPGA)

Network

100M/1G Interface,switch VLAN

USB:

USB2.0 Engine Development

CPU:

RISC-V CPU 32bit Ecosystem Dvelopment and Educational Experiments

Artificial Intelligence

Voice collection, speech recognition Image acquisition and image recognition, deep learning

1、Design Objective of the System

The main purpose of this system design is to complete FPGA learning, development and experiment with Intel Quartus. The main device uses the Inte Cyclone10 10CL040YF484C8G and is currently the latest generation of FPGA devices from Intel. The major learning and development projects can be completed as follows:

  1. Basic FPGA design training
  2. Construction and training of the SOPC (NiosII) system
  3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
  4. Development and application based on RISC-V
  5. The system is specifically optimized for hardware design for RISC-V system applications

2、System Resource

  1. Extended memory: Two Super Sram (IS61WV51216, 512K x 32bit) are connected in parallel to form a 32-bit data interface, and the maximum access space is up to 2M bytes.
  2. Serial flash: Spi interface serial flash (16M bytes)
  3. Serial EEPROM
  4. Gigabit Ethernet: 100/1000 Mbps
  5. USB to serial interface: USB-UART bridge

 

3、Human-computer Interaction Interface

  1. 8 DIP switches
  2. 8 push buttons, definition of 7 push buttons: MENU, UP, RETUN, LEFT, OK, RIGHT, DOWN, 1 for reset: RESET
  3. 8 LEDs
  4. 6 7-segment LED display
  5. I2C bus interface
  6. UART external interface
  7. Two JTAG programming interfaces: One is for downloading the FPGA debug interface, and the other is the JTAG debug interface for RISC-V CPU
  8. Built-in RISC-V CPU software debugger, no external RISC-V JTAG emulator required
  9. 4 12-pin GPIO connectors, in line with PMOD interface standards

 

4、Software Development System

  1. Quartus 18.0 and later version for FPGA development, Nios-II SOPC
  2. Freedom Studio-Win_x86_64 software development for RISC-V CPU

 

5、Supporting Resources

RISC-V JTAG Debugger

Intel Altera JTAG Download Debugger

FII-PRA040 User Experimental Manual

FII-PRA040 Hardware Reference Guide

6、Physical Picture

PRA040 system block diagram

 

PRA040 Physical front view

PRA040 Physical Back View

 

Corresponding to the physical picture, the main devices on board are as follows:

1、10CL040YE484C8G chip

2、External 12V power interface

3、GPIO interface

4、Thermistor (NTC-MF52)

5、Photoresistor

6、Potentiometer

7、Audio output (green), audio input (red)

8、PCIE interface

9、TFTCLD interface

10、Audio chip (WM8978)

11、7 push buttons

12、50M system clock

14、Video chip(ADV7511)

15、External JTAG download interface

16、HDMI interface

17、USB power supply and download interface

18、FPGA and RISC_V JTAG download chips (FT2232)

19、USB_UART interface

20、Serial chip (CP2102)

21、6 7-segment LED display

22、Ethernet interface

23、Ethernet PHY chip (RTL8211E-VB)

24、4 USB interfaces

25、USB mouse and keyboard control chip

26、8 LEDs

27、8-bit DIP switch

28、Reset button

29、Power button

30、Flash (N25Q128A,128M bit/16M bytes)

31、EEPROM (AT24C02N)

32、Two SRAMs

33、AD/DA conversion chip (PCF8591)

 

The Altera Risc-V FPGA Board Tutor – PRA040

For DPF instruction how to code in Risc-V board, please check the product pages. If you buy one of our products, we will send you detail updated instruction step by step.

Click to Buy Altera Risc-V FPGA Board 

 

RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university.

As of March 2019, version 2.2 of the user-space ISA is frozen, permitting most software development to proceed. The privileged ISA is available as draft version 1.10. A debug specification is available as a draft version 0.13.1

What is the license model of RISC-V?

The RISC-V ISA is free and open with a permissive license for use by anyone in all types of implementations. Designers are free to develop proprietary or open source implementations for commercial or other exploitations as they see fit. The RISC-V Foundation encourages all implementations that are compliant to the specifications.Note that the use of the RISC-V trademark requires a license which is granted to members of the RISC-V Foundation for use with compliant implementations. The RISC-V specification is based around a structure which allows flexibility with modular extensions and additional custom instructions/extensions. If an implementation was based on the RISC-V specification but includes modifications beyond this framework, then it cannot be referenced as RISC-V. https://riscv.org/faq/