FPGA Development Board Products

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AD9361 and AD9361 RF Transceiver™

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

AD9361 RF Agile Transceiver™ (BD9361) is a high-speed analog module designed to showcase the AD9361, a high performance, highly integrated RF transceiver intended for use in RF applications, such as 3G and 4G base station and test equipment applications, and software defined radios. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.

The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor or FPGA. The AD9361 chip operates in the 70 MHz to 6 GHz range, covering most licensed and unlicensed bands. The chip supports channel bandwidths from less than 200 kHz to 56 MHz by changing sample rate, digital filters, and decimation, which are all programmable.

For More information, please check AD9361 RF Agile Transceiver™, AD9316 Development Board

AD9361 Development Board
AD9361 RF Agile Transceiver™, AD9361 Development Board

JTAG

JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.

Processors often use JTAG to provide access to their debug/emulation functions and all FPGAs and CPLDs use JTAG to provide access to their programming functions.

JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses.

The interface connects to an on-chip test access port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.

The JTAG standards have been extended by many semiconductor chip manufacturers with specialized variants to provide vendor-specific features.

The debug and programming tools commonly associated with JTAG only make use of one aspect of the underlying technology – the four-wire JTAG communications protocol.

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