FII-CPU (RV32G2.0)

We have our own IPcore FII-CPU (RV32G) and it will be taped out soon.

The main features of our IPcore :

  1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
  2. 3-stage pipeline architecture
  3. support machine mode only
  4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
  5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
  6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
  7. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
  8. 2 UART
  9. 3 QSPI
  10. I2C
  11. PWM
  12. 10M/100M/1G ethernet
  13. Watchdog
  14. 32 GPIO
  15. 4 7-seg display interface
  16. External Serial Flash
  17. Debug Interfaces: JTAG
  18. 12-Bit ADC
  19. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
  20. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

A lot of our Risc-V experiments and our Risc-V courses are based on our own FII-CPU on our FII-PRX100 platform:


If you are interested in our Risc-V CPU chips, please contact us.