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RISC-V Board ( ARTIX 100T, XC7A100T ) – FII-PRX100-D – Xilinx Risc-V FPGA Board ( RISC-V SOPC AI Xilinx artix-7 DRAM)

$429.00 $328.00

FII-PRX100-D Risc-V FPGA Board is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Description

FII-PRX100-D Risc-V FPGA Board is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

FII-PRX100-D Risc-V FPGA Board is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Xilinx.  It was designed to cover all aspects of FPGA Development and Experiment, RISC-V SOC .  The main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc.

Features:

  1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
  2. 3-stage pipeline architecture
  3. support machine mode only
  4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
  5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
  6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
  1. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
  2. 2 UART
  3. 3 QSPI
  4. I2C
  5. 3 PWM
  6. 10M/100M/1G ethernet
  7. Watchdog
  8. 32 GPIO
  9. 4 7-seg display interface
  10. External Serial Flash
  11. Debug Interfaces: JTAG
  12. 12-Bit ADC
  13. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
  14. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

The entire system is designed by the verilog language, and all IPs can be added, deleted and reconfigured.

FII-PRX100T-D DDR Version
FII-PRX100-D DDR Version
FII-PRX100-S SRAM Version
FII-PRX100-S SRAM Version

The FII-PRX100-D RISC-V development board introduction

  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertor, QSPI flash, I2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO , hdmi transmitter and camera etc.

RISC-V IPCore user development Guide

This document is edited by Fraser Innovation Inc. Step by step introduce how to develop each RISC-V CPU RTL modules based on RISC-V ISA, Simulations and board verifications, software environment and details on C language development, debug and program

Artificial Intelligence

Voice collection, speech recognition
Image acquisition and image recognition, deep learning

IOT

FII-PRX100-D Risc-V FPGA Board Product Features:

  • FPGA part:  XC7A100T-2FGG676I
  • 1MSPS On-chip:  yes
  • Logic Cells:  101440
  • Logic Slices: 15850
  • Flip-flops: 65200
  • Memory blocks(36K): 135
  • Memory block(Kb): 4860
  • Clock Management Tiles: 6
  • DSP Slices: 240

System Features:

  • ADC: On-chip analog-to-digital converter (XADC)
  • DRAM: DDR3 MT41J128M16HA-125  ( Micron Technology LTD )
  • Clock Frequency: 800MHZ
  • Memory Size: 2GB (128M X 16)
  • Spi Flash serial flash (16M bytes)
  • JTAG:  jtag Programmable ports
  • Multifunction: used for other board  (For example: iMX226 camera board, or adv7612 Hdmi in board , etc)
  • Power Supply: 12V adapter source

Interaction and Sensory Devices:

  • 8 Switches
  • 7 Buttons (up , down, left, right, ok, menu, return)
  • 1 Reset button
  • 8 LEDs
  • 1 4-digit 7 segment display
  • 1 I2c interface (24c02 eeprom)
  • Expansion Connector:

  • 4 gpio connectors (compatible with digilent Pmod)
  • 2 MultiFunction connectors (connect with iMX226 board, or others
  • Main Chips: xilinx (1.0mm pitch) XC7A100T_FGG676

Interaction and Sensory Devices

  • GPIO Interface  (16 ) 2×8 Standard 2.54mm connector (pin)
  • led output  (8 ) 0603 SMD
  • 8 switchs SMD
  • 7 buttons (Top, Bottom, left, right,center, top left (menu), top right (return)
  • i2c 24c02 smd soic
  • spi flash MX25L6433F 8-SOP (8M bytes)
  • usb2uart ft2232C/H (2 uart ) Or cp2102 (1  uart)
  • jtag 2×5 Standard 2.54mm connectors(pin)
  • eth 1G CAT5 Ethernet (rtl8111e)
  • sram IS61WV25616 (2 pieces ) 256K x 32bit
  • Digital tube 7seg (4) oasistek TOF-5421BMRL-N 
  • Hdmi out adv7511hdmi_adv7511.SchDoc
  • Test Port: 1×6 Standard2.54mm Connectors (pin)

We will send you following Documents after you have bought from us:

Risc-V Board PRX100-D Experimental Manual

Risc-V Board PRX100-D Schematic Diagram

Risc-V Board PRX100-D Hardware Configuration

FII-PRX100-D Development Board ( ARTIX 100T, XC7A100T, RISC-V FPGA Developing Board)

Online Shopping:

https://fpgamarketing.com/FII-PRX100-D-ARTIX-100T-XC7A100T-RISC-V-FPGA-Board-PRX100-D-1.htm

  1. FII-PRX100-D RISC-V development board

    1. Suitable for FPGA study and training
    2. Fully support FIE310 CPU running and system development
    3. Suitable for user customized RV32G verification and validation
    4. JTAG interface for FPGA and FIE310 CPU download and debug
    5. Support Windows software and linux development environment
    6. GCC compilation toolchain and graphical software development environment
    7. Hardware resource: Switchs, Push Button ,USB to UART convertorQSPI flash, I2CEEPROM, 100M/1G ethernet,USB keyboard mouse,GPIOhdmi transmitter and camera etc.

    1.System Design Objective

    The main purpose of this system design is to complete FPGA learning, development and experiment with Xilinx-Vivado. The main device uses the Xilinx-XC7A100T-2FGG676I and is currently the latest generation of FPGA devices from Xilinx. The main learning and development projects can be completed as follows:

    1. Basic FPGA design training
    2. Construction and training of the SOPC (Microblaze) system
    3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
    4. Development and application based on RISC-V
    5. The system is specifically optimized for hardware design for RISC-V system applications.

2.System Resource

    1. Extended memory
    2. Use two Super Srams in parallel to form a 32-bit data interface with a maximum access space of 1M bytes.
    3. IS61WV25616 (2 pieces) 256K x 32bit
    4. Serial flash
    5. Spi interface serial flash (128M bytes)
    6. Serial EEPROM
    7. Gigabit Ethernet: 100/1000 Mbps
    8. USB to serial interface: USB-UART bridge

3.Human-computer Interaction Interface

    1. 8 toggle switches
    2. 8 push buttons
    3. Definition of 7 push buttons: up, down, left, right, ok, menu, return
    4. 1 for rest: Reset button
    5. 8 LEDs
    6. 6 7-segment decoders
    7. I2C bus interface
    8. UART external interface
    9. JTAG programming interfaces
    10. Integrated FPGA Jtag and Risc-V Jtag by using single USB port.
    11. Built-in RISC-V IPCore
    12. CPU software debugger, no external RISC-V JTAG emulator required
    13. 12-pin GPIO connectors, in line with PMOD interface compatible.

Software Development System

  1. Vivado 18.1 and later version for FPGA development, Microblaze SOPC
  2. Freedom Studio-Win_x86_64 Software development for RISC-V CPU

5.  Supporting Resources

    1. RISC-V  JTAG Debugger
    2. Xilinx Altera JTAG Download Debugger
    3. FII-PRX100-D Development Guide
PRX100 Development Board Full View
PRX100 Development Board Full View

The Artix-7 is one of the Xilinx 28nn FPGA families. It features a small form factor package that reduces the power consumption of the Artix-7 family by half compared to the Spartan-6 family.

PRX100 system block diagram:

prx100 system block diagram

PRX100 Hardware resources

  • It can be powered by external 12V DC source or by “USB Power Supply and Download Interface”. The latter also provides program download functionality. Only one wire is to complete the power supply and download functions;
  • A 50 MHz oscillator, a 32.768 kHz oscillator, provides a stable clock source for the development board;
  • 6-digit common anode 7-segment decoders, through dynamic scanning to achieve data display;
  • 1 HDMI interface displaying color pictures or camera video;
  • 1 chip I2C interface EEPROM chip, model AT24C02;
  • 1 adaptive 10 M/100M/Gigabit Ethernet interface;
  • 8 push buttons, 7 for programmable buttons, 1 for reset button;
  • 1 photoresistor, through which it can simulate light control; 1 thermistor, which can collect temperature or analog temperature alarm function; 1 potentiometer, which can simulate voltage change;
  • 1 PCF8591 AD/DA conversion chip, reserved external interface, free input and output;
  • Onboard 50MHz and 32.768kHz oscillators provide stable clock signals to the development board;
  • 8-bit DIP switch;
  • 8-bit LED;
  • 1 128Mbit Flash chip;
  • 4 GPIO external signal expansion interfaces, also the PMOD standard interface;
  • A 40-pin GPIO expansion interface that provides a large amount of I/O for developers to use freely;
  • Two JTAG interfaces, one for the FPGA download debug interface (J4, J5) and one for the RISC-V CPU JTAG debug interface(J16). Built-in RISC-V CPU software debugger, no external RISC-V JTAG emulator required;
  • 1 UART asynchronous serial interface;
  • 2 SRAMs with a capacity of 8Mbit;
  • a pair of audio input and output interfaces;
  • 1 PCIE interface;
  • 4 USB interfaces, 2 for the mouse and keyboard interface, 2 for the universal serial interface;
  • 1 USB (USB-B) to UART interface for serial communication;
  • 1 TFTLCD touch screen interface, which can realize the display and operation of the touch screen;

RISC-V FPGA Board – FII-PRX100-S Experimental Manuals – Study Guide (V1.1)

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