Altera Risc-V FPGA Board Risc-V SOPC AI Cyclone10 – FII-PRA040 – Risc-V Educational Platform With 19 Experimental Manuals



FII-PRA040 RiscV Educational Platform is a ready-to-use development platform designed around the Field Programmable Gate Array (FPGA) from Intel Altera. RISC-V (pronounced “risk-five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles.

Altera RISC-V SoC AI FPGA Development Board Educational Platform
Altera RISC-V SoC AI FPGA Development Board Educational Platform
Altera RISC-V SoC AI FII-PRA040 Educational Platform
Altera RISC-V SoC AI FII-PRA040 Educational Platform

It was designed for use in all fields of FPGA development and experiments.


Digital Communication DSP(FPGA)


100M/1G Interface,switch VLAN


USB2.0 Engine Development


RISC-V CPU 32bit Ecosystem Dvelopment and Educational Experiments

Artificial Intelligence

Voice collection, speech recognition Image acquisition and image recognition, deep learning


  10CL040 10CL080
Logic elements (LEs) (K) 40 80
Memory blocks(9K) 126 305
LMemory block(Kb) 1134 2745
18×18 multipliers 126 244
Phase-locked loop(PLL) 4 4
Global clock networks 20 20


System Features:

    • Sram IS61WV25616 (2 pieces ) 256K x 32bit
    • Spi serial flash (16M bytes)
    • JTAG:  two jtag programmable interfaces
    • power Supply: 12V adapter source

System Connectivity

  1. 10/100/1000 Mbps Ethernet
  2. Hdmi: Hdmi out (1920×1080@60Hz)
  3. USB to Serial Interface:USB-UART bridge


Interaction and Sensory Devices

  1. 8 Switches
  2. 7 Buttons (up , down, left, right, ok, menu, return)
  3. 1 Reset button
  4. 8 LEDs
  5. 1 4-digit 7 segment display
  6. 1 I2c interface (24c02 eeprom)
  7. High resolution graphic LCD interface
  8. Image input interface

Expansion Connectors

    • 4 gpio connectors (compatible with digilent Pmod)

Features and Benefits  

  1. gpio  (16 ) 2×8 standard 2.54mm connectors (pin)
  2. led  outport (8 ) 0603 smd
  3. switch (8 in one group) smd 
  4. 7 Buttons (up , down, left, right, ok, menu, return)
  5. i2c  24c02 smd soic
  6. spi  flash MX25L6433F 8-SOP (8M bytes)
  7. usb2uart ft2232C/H (2 uart ) Or cp2102 (1  uart)
  8. jtag 2×5 standard 2.54mm connectors(pin)
  9. eth  1G CAT5 Ethernet (rtl8111e)
  10. Digital tube 7seg (4) oasistek TOF-5421BMRL-N
  11. Hdmi out adv7511hdmi_adv7511.SchDoc
  12. Test Port1×6 Standard 2.54mm connector (pin)

This image has an empty alt attribute; its file name is alterapinport.png


    1. The Pins must be connectted by above picture, and you cannot change the sequence
    2.  TEST_3V3_PIN* must be 3.3V gpio
    3. Power supply adpter:  5.3V adapter 2.6A 5mm X 2.5mm Interface jack
    4. Power module:  RT8068, RT8088, etc (for 1.2v, 1.8v, 2.5v, 3.3v ) 
    5. Size : 21.4cm x 14 cm (Half  A4 )


Official Shopping Website:


Altera Xilinix RISC-V SoC AI FII-PRA040 Educational Platform – front view
Altera Xilinix RISC-V SoC AI FII-PRA040 Educational Platform – back View


Altera Xilinix RISC-V SoC AI FII-PRA040 Educational Platform – Side View


We will send you following documents after you have bought our products:


PRA040 Hareware Configuration Reference Guide

PRA040 Schematic Diagram

Altera Risc-V User Experimental Manual – PRA040

More Information about PRA040 Altera Risc-V FPGA Board.

1、Design Objective of the System

The main purpose of this system design is to complete FPGA learning, development and experiment with Intel Quartus. The main device uses the Inte Cyclone10 10CL040YF484C8G and is currently the latest generation of FPGA devices from Intel. The major learning and development projects can be completed as follows:

  1. Basic FPGA design training
  2. Construction and training of the SOPC (NiosII) system
  3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
  4. Development and application based on RISC-V
  5. The system is specifically optimized for hardware design for RISC-V system applications

2、System Resource

  1. Extended memory: Two Super Sram (IS61WV51216, 512K x 32bit) are connected in parallel to form a 32-bit data interface, and the maximum access space is up to 2M bytes.
  2. Serial flash: Spi interface serial flash (16M bytes)
  3. Serial EEPROM
  4. Gigabit Ethernet: 100/1000 Mbps
  5. USB to serial interface: USB-UART bridge


3、Human-computer Interaction Interface

  1. 8 DIP switches
  2. 8 push buttons, definition of 7 push buttons: MENU, UP, RETUN, LEFT, OK, RIGHT, DOWN, 1 for reset: RESET
  3. 8 LEDs
  4. 6 7-segment LED display
  5. I2C bus interface
  6. UART external interface
  7. Two JTAG programming interfaces: One is for downloading the FPGA debug interface, and the other is the JTAG debug interface for RISC-V CPU
  8. Built-in RISC-V CPU software debugger, no external RISC-V JTAG emulator required
  9. 4 12-pin GPIO connectors, in line with PMOD interface standards


4、Software Development System

  1. Quartus 18.0 and later version for FPGA development, Nios-II SOPC
  2. Freedom Studio-Win_x86_64 software development for RISC-V CPU


5、Supporting Resources

RISC-V JTAG Debugger Intel Altera JTAG Download Debugger FII-PRA040 User Experimental Manual FII-PRA040 Hardware Reference Guide


6、Physical Picture

PRA040 system block diagram   PRA040 Physical front view PRA040 Physical Back View  

Corresponding to the physical picture, the main devices on board are as follows:

1、10CL040YE484C8G chip

2、External 12V power interface

3、GPIO interface

4、Thermistor (NTC-MF52)



7、Audio output (green), audio input (red)

8、PCIE interface

9、TFTCLD interface

10、Audio chip (WM8978)

11、7 push buttons

12、50M system clock

14、Video chip(ADV7511)

15、External JTAG download interface

16、HDMI interface

17、USB power supply and download interface

18、FPGA and RISC_V JTAG download chips (FT2232)

19、USB_UART interface

20、Serial chip (CP2102)

21、6 7-segment LED display

22、Ethernet interface

23、Ethernet PHY chip (RTL8211E-VB)

24、4 USB interfaces

25、USB mouse and keyboard control chip

26、8 LEDs

27、8-bit DIP switch

28、Reset button

29、Power button

30、Flash (N25Q128A,128M bit/16M bytes)

31、EEPROM (AT24C02N)

32、Two SRAMs

33、AD/DA conversion chip (PCF8591)

Atera Risc-V FII-PRA040 Experimental Manuals ( 1- 20 ) PDF Version 304 Pages

FII-PRA040 Hardware Configuration 


FII-PRA040 Schematic Diagram 



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