FII-PRA040

Building FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II, Block/SCH – FII-PRA040 Risc-V FPGA Board Experimental 4

August 8, 2019July 10, 2020 SteveGuysdevice selection, FII-PRA040, FPGA projects, PLL creation, PLL frequency setting, Quartus, SignalTap II, Verilog tree hierarchy

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3,…