Altera Risc-V FPGA Tutorial : Segment Display
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Altera Risc-V FPGA Tutorial : Block/SCH – FII-PRA040 FPGA Board Experimental 4

Experiment 4 Block/SCH

4.1 Experiment Objective

  1. Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II
  2. Master the design method of graphics from top to bottom
  3. Combined with the BCD_counter project to achieve the display of the digital clock
  4. Observe the experimental results

4.2 Experiment Implement

Use schematics design to build the project.

4.3 Experiment

This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3, and will not be introduced in detail. The modular design method is introduced below.

  1. New project: File -> New Project Wizard

Project name: block_counter

Select device (10cl010YE144c8G)

  1. Create nre file; File -> New, select Blcok Diagram/Schematic File. See Figure 4.1.

Figure 4.1 New file

  1. Create as shown in Figure 4.2, the middle part is the graphic design area, which can be used for Block/SCH design.
  2. Save the file as block_counter.bdf
  3. Double-click the blank space in the graphic design area to add a symbol

 

Altera Risc-V FPGA Board Block/SCH Experiment
Altera Risc-V FPGA Board Block/SCH Experiment

Figure 4.2 Graph design interface

  1. Graphic editing

-click on the graphic design area to select the appropriate library and device in the libraries

 

  1. Add input, output, and modify their names
  2. Add a custom symbol
  3. Create a new block/sch file and store it as PLL_sys.bdf
  4. Add PLL IP, refer to experiment 1
  5. Select the generated file to include the PLL1.bsf file
  6. Double-click in the blank area of the PLL_sys.bdf file to select the PLL1 symbol just generated and add it to the file, as shown in Figure 4.4.

Figure 4.4 Invoke the symbols generated in the IP catalog in the graphical editing interface

  1. Continue to add other symbols, input, output, dff, GND, etc. and connect them, as shown in Figure 4.5.

Figure 4.5 Connect the device

  1. Recreate the newly created file symbol for graphic editing to use in subsequent design
  2. File -> Create/Update -> Create Symbol file for Current File. See Figure 4.6.
  3. Generate PLL_sys.bsf

Figure 4.6 Creating a symbol file for the current file (symbol file *.bsf)

  1. Create a frequency division module
  2. Create a new verilog file div_us for the divider (Refer project files for the code)
  3. The PLL output clock is used as its own input clock, and the 100 MHz clock is divided into 1 MHz clocks.
  4. Repeat (7) to create div_us.bsf
  5. Create a new 1000 frequency division verilog file: div_1000f.v
  6. Create div_1000f.bsf symbol
  7. Create the output pulse us, ms, second module, as shown in Figure 4.7. Refer the specific implementation to the reference code and the frequency division design of the experiment 1 and 3
  8. Create a new block/sch file block_div and add the designed graphic symbol file to block_div.bdf
  9. Repeat (7) to create the block_div.bsf symbol

Figure 4.7 us, ms, second pulse of block/sch design

  1. Create a new verilog file bcd_counter.v, design the hour and minute counter, and create the bsf symbol. Refer to experiment 3, and implement part of the frequency division using block_div in (9).
  2. Combine each *.bsf and complete the design of the digital clock (block_counter.bdf), as shown in Figure 4.8.

Figure 4.8 Digital clock for BDF design

4.4 Experiment Verification

Pin assignment, compilation, and program verification are consistent with Experiment 3. For reference, see Experiment 3, which is elimibated here.

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