FII RISC-V3.01 CPU FII-PRA040 FII-PRX100-S FII-PRX100D Risc-V Risc-V Core Risc-V Tutorial

RISC-V Instruction Set Explanation

V1.0 Fraser Innovation inc RISCV instruction set explanation Version Control Version Date Description V1.0 2020/11/27 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how to use the product correctly. Improper…

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Graphic Design Interface
Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Combined With the BCD_Counter Project to Achieve the Display of the Digital Clock, Master the Design Method of Graphics From Top to Bottom – Block/SCH – Altera Risc-V Board PRA040 Experimental 4

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3…

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Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V Risc-V Core

Frequency Division Design, Learn the BCD Code Counter, Digital Display Decoding Design, Segment Display – Altera Risc-V Board PRA040 Experimental 3

Experiment 3 Segment Display 3.1 Experiment Objective Review experiment 1, proficient in PLL configuration, frequency division design, and project verification; Learn the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. The decimal point remains off and will not be considered for the time being. 3.3 Experiment 3.3.1 Introduction to the…

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FII RISC-V3.01 CPU FII-PRA040 Risc-V Risc-V Core

Learn to Analyze the Captured Signals, Practice the Use of SignalTap Logic Analyzer in Quartus – SignalTap – Altera Risc-V Board PRA040 Experimental 2

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice the use of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Use switches to control the LED light on and off Capture and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction of DIP Switches and SignalTap Introduction of switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the…

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Experimental Manuals FII RISC-V3.01 CPU FII-PRA040 FPGA Tutor Risc-V Risc-V Core

Master the Design of the Frequency Divider to Implement the Shifting – LED LED Shifting – Altera Risc-V Board PRA040 Experimental 1

Experiment 1 LED shifting 1.1 Experiment Objective Practice to use Quartus II to create new projects and use system resources IP Core; Proficiency in the writing of Verilog HDL programs to develop a good code writing style; Master the design of the frequency divider to implement the shifting LED; Combine hardware resources to perform FPGA pin assignment and implement actual program downloading; Observe the experiment result and summarize it. 1.2 Experiment Implement Use all LEDS, all light up during reset; End reset, LED lights from low to high (from right…

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FII RISC-V3.01 CPU FII-PRA040 FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

C Programming (2) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board C Programming 2 Version Control Version Date Description 1.0 10/17/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

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FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D FPGA Board Based FPGA Tutor PRX100 Risc-V Risc-V Core Risc-V Tutorial

C Programming (1) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board C Programming 1 Version Control Version Date Description 1.0 10/24/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

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FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

Risc-V Bus and PipeLine – FII Risc-V Bus and Pipeline Design – Risc-V Tutorial and Exercise

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board Bus and Pipeline Version Control Version Date Description 1.0 10/28/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

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Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Evaluation by Coremark and Dhrystone Benchmarks

V1.1 Fraser Innovation inc FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Evaluation Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/07/2020 Add Description of PRX100 and Comparison Plots Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using…

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Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

Dhrystone Porting Guide For FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board

V1.1 Fraser Innovation inc Dhrystone Porting Guide For FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/07/2020 Add Description of PRX100 and Comparison Plot Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual…

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