FPGA projects

Building FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II, Block/SCH – FII-PRA040 Risc-V FPGA Board Experimental 4

August 8, 2019July 10, 2020 SteveGuysdevice selection, FII-PRA040, FPGA projects, PLL creation, PLL frequency setting, Quartus, SignalTap II, Verilog tree hierarchy

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3,…

FPGA for Beginners FPGA Tutor PRA006/PRA010

interface types (MII, GMII, RGMII) advantages and disadvantages – Ethernet Experiment – FPGA Board for Beginner – Experiment 14

July 22, 2019August 11, 2020 SteveGuysEthernet, Ethernet project verilog code, FPGA Board for Beginner, FPGA projects, Gigabit NIC, GMII, interface types, MII, MII interface, RGMII

Experiment 14 Ethernet Experiment 14.1 Experiment Objective Understand what Ethernet is and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (our development board uses RGMII) Combine the development board to complete the transmission and reception of data and verify 14.2 Experiment Requirement Perform a loopback test to check if the hardware is working properly. Performing data verification Perform data transmission verification 14.3 Experiment 14.3.1 Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method that…