Prx100

Understand the register configuration of the ADV7511, HDMI Graphic Display Experiment – Xilinx Risc-V Board Tutorial : FII-PRX100 FPGA Board Experiment 14

July 29, 2019August 6, 2020 SteveGuysADV7511, HDMI Graphic Display, Prx100, Risc-V, Xilinx

Experiment 14 HDMI Graphic Display Experiment 1.Experiment Objective Learn about video timing (2) Understand the register configuration of the ADV7511, reviewing the knowledge from experiment 12 2.Experiment Requirement Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. Display the image using the HDMI interface of the development board. Download the program to the board for comparison. Introduction to HDMI:…

Experimental Manuals FPGA Tutor PRX100 Risc-V

digital-to-analog conversion: DAC, analog-to-digital conversion: ADC – Xilinx Risc-V Board Tutorial : AD, DA Experiment – FII-PRX100 FPGA Board Experiment 13

July 29, 2019July 31, 2020 SteveGuysAD, DA Experiment, PCF8591, Prx100, Risc-V, Xilinx

Experiment 13 AD, DA Experiment 1.Experiment Objective Since in the real world, all naturally occurring signals are analog signals, and all that are read and processed in actual engineering are digital signals. There is a process of mutual conversion between natural and industrial signals (digital-to-analog conversion: DAC, analog-to-digital conversion: ADC). The purpose of this experiment is twofold: Learning the theory of AD conversion Read the value of AD acquisition from PCF8591, and convert the value obtained into actual value, display it with segment decoders 2.Experiment Requirement Perform analog-to-digital conversion using…

ModelSim simulation waves sent by serial

Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Asynchronous Serial Port Design and Experiment – FII-PRX100 FPGA Board Experiment 11

July 29, 2019February 9, 2020 SteveGuysAsynchronous Serial Port Design, Prx100, Risc-V

Experiment 11 Asynchronous Serial Port Design and Experiment 1.Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 2.Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start bit,…

Risc-V Board - Dual_port RAM test result

Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Use Dual_port RAM to Read and Write Frame Data – FII-PRX100 FPGA Board Experiment 10

July 29, 2019January 11, 2020 SteveGuysPrx100, Risc-V

Experiment 10 Use Dual_port RAM to Read and Write Frame Data 1.Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Observing the synchronization structure of synchronous clock frames using ILA Extended the use of dual-port RAM Design the use of three-stage state machine 2.Experiment Requirement Generate dual-port RAM and PLL 16-bit width, 256-depth dual-port RAM 2 PLL, both 50 MHz input, different 100 MHz and 20…