Experiment 16 8978 Audio Loopback Experiment
- Learn about I2S (Inter-IC Sound) bus and how it works
- Familiar with the working mode of WM8978. And by configuring the interface mode and selecting the relevant registers in combination with the development board, complete the data transmission and reception, and verify it
- Perform audio loopback test by configuring the onboard audio chip WM8978 to check if the hardware is working properly
- Adjust the volume output level with the push buttons.
16.3.1 WM8978 Introduction
WM8978 is a low power, high quality stereo multimedia digital signal CODEC introduced by Wolfson. It is mainly used in portable applications such as digital cameras and camcorders. Advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal Automatic Level Control for the microphone or line input through the ADC as well as a purely digital limiter function for record or playback. Additional digital filtering options are available in the ADC path, to cater for application filtering, such as “wind noise reduction”.
See Figure 16.1 for the internal structure block diagram of WM8978.
Figure 16.1 WM8978 internal structure block diagram
Figure 16.2 Schematics of the audio part of the development board
16.3.2 WM8978 Control Interface Timing
The WM8978 control interface has two-wire mode and three-wire mode. The specific mode is selected by the MODE pin connection of WM8978. When the mode pin is connected to a low voltage level, it is a two-wire mode, and when it is connected to a high voltage level, it is a three-wire mode. The development board mode pin is grounded. When the control interface is in two-wire mode, the timing diagram is shown in Figure 16.3. The timing diagram is the same as the IIC timing. The device address of WM8978 is fixed to 7’b0011010. This chip register only supports writing and does not support reading.
Figure 16.3 Timing diagram of the two-wire mode interface
16.3.3 I2S Audio Bus Protocol
I2S (Inter-IC Sound Bus) is just a branch of PCM, the interface definition is the same, I2S sampling frequency is generally 44.1KHz and 48KHz, PCM sampling frequency is generally 8K, 16K. There are four groups of signals: bit clock signal, synchronization signal, data input, data output.
I2S is a bus standard developed by Philips for audio data transmission between digital audio devices. In the Philips I2S standard, both the hardware interface specification and the format of digital audio data are specified. I2S has three main signals: the serial clock SCLK, also known as the bit clock BCLK, which corresponds to each bit of data of digital audio. The frequency of SCLK = 2 × sampling frequency × sampling number of bits. The frame clock LRCK is used to switch the data of the left and right channels. An LRCK of “0” indicates that data of the left channel is being transmitted, and “1” indicates that data of the right channel is being transmitted. LRCLK == FS, is the sampling frequency serial data SDATA, which is audio data expressed in two’s complement. Sometimes in order to enable better synchronization between systems, another signal MCLK is needed, which is called the master clock, or also called the system Clock (System Clock). It is 256 or 384 times the sampling frequency.
The timing of the I2S protocol is shown in Figure 16.4. However many bits of data the I2S format signal has, the most significant bit of the data always appears at the second BCLK pulse after the LRCK change (that is, the beginning of a frame). This allows the number of significant digits at the receiving end and the transmitting end to be different. If the receiving end can process less significant bits than the transmitting end, the extra low-order data in the data frame can be discarded; if the receiving end can process more significant bits than the transmitting end, it can make up the remaining bits by itself. This synchronization mechanism makes the interconnection of digital audio equipment more convenient without causing data errors.
Figure 16.4 I2S timing protocol
16.3.4 Main Program Design
- WM8978 register configuration program
Only the program of register configuration program is given here, please refer to the project file for the complete program
- Audio signal acquisition program
- Audio sending module
- Main program
- Pin assignment
Table 16.1 Pin assignment
|Signal Name||Port Description||Network Name||FPGA Pin|
|Sys_clk_50||System 50M clock||C10_50MCLK||U22|
|Reset_n||System reset signal||KEY1||M4|
|Wm_sdin||8978 register configuration data line||I2C_SDA||R21|
|Wm_sclk||8978 register configuration clock||I2C_SCL||R20|
|Wm_lrc||8978 align clock||WM_LRCK||H15|
|Wm_bclk||8978 bit clock||WM_BCLK||F18|
|adcdat||ADC input of 8978||WM_MISO||G19|
|Dacdat||DAC input of 8978||WM_MOSI||F20|
|Mack||PLL provides 8978 working master clock||WM_MCLK||H17|
|Key1||Volume up button||Key2||L4|
|Key2||Volume down button||Key7||R7|
- Board verification
As shown in Figure 16.5 below, after the FPGA development board is programmed, use a dual male audio cable, with one end plugged into the red audio receiver end and the other end plugged into a music player. Plug the headphone into the green audio playback port. The music can be heard from player. The volume is divided into 5 gears. Press the UP key to increase the volume and press the down key to decrease the volume.
Figure 16.5 wm8978 board verification