- Continue to practice using develop board
- Learn to use ILA (Integrated Logic Analyzer) in Vivado
- Learn to use the FPGA configuration memory for programming
- Refer to Experiment 1
- Select the same chip in Experiment 1
- Add PLL1 (Here PLL1 is optional, external input clock can be used directly)
input [7:0] sw,
output reg[7:0] led
always @(posedge inclk)
Schematics of develop board
- See Fig 2. 1. the diodes D19-D26 are mainly used to eliminate the damage of the FPGA pin caused by human body contact static electricity.
Fig 2. 1 Switches drive the circuit
|Signal Name||Port Description||Network Label||FPGA Pin|
|inclk||System Clock 50 MHz||C10_50MCLK||U22|
|rst||Reset, high by default||KEY1||M4|
6.Download to the develop board to test and dial the DIP switch to see the corresponding LED light on and off. See Fig 2. 2.
Fig 2. 2 Experiment result
- Choose top-level entity SW_LED.v file to Run Synthesis
- After the integration is complete, under the Netlist window, all network nodes present in the current design are listed. Debug the network nodes. See Fig 2. 3.
Fig 2. 3 Mark debugged network nodes
- In the Vivado main interface menu, execute the menu command Tool -> Set up Debug. In the popup window, there is clock domain of the selected debug signal. The clock domain of sw_IBUF is red. See Fig 2. 4.
Fig 2. 4 Debugged network node clock domain setting
- In the red circle shown in Fig 2. 4, right click to set the clock domain.
Fig 2. 5 Modify the debugged network node clock domain
- After the setting is completed, click Next. The popup window is shown in Fig 2. 6. Set the data collection depth and select the check box in front of Capture control and Advance trigger. Then keep clicking Next until the end.
Fig 2. 6 Set the data collection depth
- Add I/O pin constraint information for implementation. Then generate a bit file and download it to FPGA. The debugging interface is automatically popped up. Click the icon button to see the following results. The test results in the debug diagram below Fig 2. 7 indicate that the design results are correct.
Fig 2. 7 Debug
When the input of switch is high, the input LED pin is controlled to be low, and the LED is lit. The figure for the experiment result on board from above shows that the input sw is 10001100 and the LED light is 01110011. The hexadecimal is 8c and 73 respectively. It is consistent with the ILA test results in the figure above.
- Modify the trigger condition to test the output under different trigger conditions