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FPGA Board Beginner Tutorial – FII-PRA006 Experiment 1 LED_shifting

1.1 Experiment Objective

  1. Practice to use development software Quartus II, including projects, system resources IP core;
  2. Proficiency in the writing of Verilog HDL, develop a fine writing style;
  3. Master the design of the frequency divider to realize the design of led shifting;
  4. Mange FPGA pin assignment according to the hardware resources;
  5. Observe the experiment result and summarize.

1.2 Experiment Requirement

  1. Light all the LEDs when resetting;
  2. After resetting, all the LEDs blink from right to left (low to high);
  3. Each led is lit for 1 second;
  4. After the last left led blinks, the most right led continue to blink, to create a blink loop.

1.3 Experiment

1.3.1 Project building

Take Quartus II 18.0 version as an example, the actual steps have been shown in figures.

The main Quartus II display
The main Quartus II display

A. In Fig 1.1, you could start a new project by clicking the New Project Wizard at the software  center, or going to File > New Project Wizard, or the shortcut Ctrl + N.

Choose The Directory
Choose The Directory

B. In Fig 1.2, set the working directory to be example/led_run. The project must have a name, a related and easy name is suggested for future use and invoke. Choose led_run for the name. Since we have not yet created the directory, Quartus II software displays the pop-up box in Fig 1.3 asking if it should create the desired directory. Click Yes, which leads to the window in Fig 1.4. Choose Empty project and click Next.

confirm create new directory
confirm create new directory
Select Project Type
Select Project Type
Add Files
Add Files

C. In Fig 1.5, you could add existing files (if any) to the project. Here, we click Next.

choose device family and a pecific device
choose device family and a pecific device

D. In Fig 1.6, choose Cyclone 10 LP for the family, Specific device selected in ‘Available devices’ list in target device and choose 10CL010YE144C8G chip in available devices. Click Next.

EDA tool settings
EDA tool settings

E. In Fig 1.7, some EDA tools are available. Here, we use default setting. Click Next and then Finish to finish the project building.

select new file type
select new file type

F. In Fig 1.8, choose File > New, Verilog HDL File and then click OK. To make the file name and project name consistent, click File > Save As, for the file name, use led_run, the type should be Verilog HDL Files. Remember to save it under the right directory.

1.3.2 PCB Schematics

pcb-schematics-for-the-leds
pcb-schematics-for-the-leds

In Fig 1.9, all the LEDs share the same high anodes, so when an external low voltage is given in cathodes, LEDs are lit up.

1.3.3 Experiment Procedure

Step 1: Main Verilog HDL code block

module LED_shifting (clk, rst, led);
input clk, rst; output [7:0] led;
endmodule

The input has clk and rst. clk is 50 MHz in this case. rst is to reset (We use PB1 on board as our reset key).

8 LEDs are defined as a vector 7 downto 0, to save the pin resources. Enter the main code to the led_run Verilog HDL file we just made.

Step 2: Invocation for IP core, building and using PLL module

1. In Fig 1. 10, find IP Catalog in the right side of the main interface.

Click Library > Basic Functions > Clocks;

PLLs and Resets > PLL > ALTPLL

IP-Catalog
IP-Catalog

2. Double click ALTPLL, and name PLL module. Here, we use PLL1, and make sure file type is Verilog, click OK. See Fig 1. 11.

Name-PLL-Module
Name-PLL-Module

3. In Fig 1. 12, PLL setting interface had popped up. Inclk0 is the input clock of PLL, provided by the original board. It should be consistent with the system clock, to be 50 MHz. Set In normal mode for the feedback path inside the PLL, and c0 is the output clock. Click Next.

PLL-setting-1-input-clock
PLL-setting-1-input-clock

4. In Fig 1. 13, optional inputs and lock output are for selecting. Here, we use the default setting.

PLL-setting
PLL-setting

5. Click Next in the next 3 steps. PLL Reconfiguration default setting are used.

6. In Fig 1. 14, Output Clocks are set. In total, 5 different clocks clk c0 – clk c4 are available. Here, only clk c0 is needed. Click Use this clock only for c0. Check the box Enter output clock frequency, set the frequency to be 100 MHz. Make sure the Clock phase shift is 0 degree, and the Clock duty cycle is 50 (%).

PLL-Setting-outputclock
PLL-Setting-output clock

7. Use the default EDA setting. Click Next.

8. In Fig 1.15, select the output file type *.bsf (will be used in the future when designing the graphic symbol design), remain the other to be the same. Click Finish.

set Output File Type
set Output File Type

9. In Fig 1.16, choose Files in the drop-down menu of Project Navigator (by default is Hierarchy).

The Location of PLL in Files
The Location of PLL in Files

10. In Fig 1. 17, click PLL1.v, the main interface will display the code for PLL, find the module name and port list, copy them to the top level file (led_run.v), and instantiate it.

Module and port list of PLL1
Module and port list of PLL1

11. Refer to the actual project files LED_shifting attached, adjust port allocation in top level file. Sys_rst is 1 before PLL, as the reset signal for the whole system. After the whole system gets locked (pll_locked == 1’b1), sys_rst is 0, and the register is driven by the rising edge of sys_clk, so it is the synchronous reset signal.

Step 3: The design of the frequency divider

code can be found in the attached project files, 100 MHz clock output by the PLL is used for the system clock. The LED light blinking period is 1 second after the frequency division.

1. Microsecond frequency division

First period of 100 MHz clock is 10 ns, 1 us needs 100 clock cycle. A register [7:0] us_reg is defined.

2. Millisecond frequency division

Since 1 ms = 1000 us, a [9:0] ms_reg is defined.

3. Second frequency division Since

1 s = 1000 ms, a [9:0] s_reg is defined, and a second pulse signal s_f. Only after these three registers are counted full at the same time, it is 1 s, and a second pulse signal is sent.

Step 4: Blinking led design

After pressing reset, all the LEDs are lit. The LED output is 8’hff, and then the LED will blink one by one from the right most (lowest).

The LED output is 8’b0000_0001, after received the pulse signal, the LED output will become 8’b0000_0010. It seems like the high voltage logical shifts left.

This could be implemented by bit splicing, that is, led <= {led [6:0], led [7]}.

Step 5: Verification

program simulation
program simulation

In Fig 1.18, click the icon to compile the program, or use the shortcut Cltr + K. The third icon on the left is Pin Planner.

The second one from the right is Programmer. A compilation report will be generated after finishing compilation, shown in Fig 1. 19.

complilation Report
complilation Report

 

After debugging, you could download the program to the board. But before that, remember to do the pin assignment in the Pin Planner by other clicking the icon stated above or go to Assignments > Pin Planner. See Fig 1. 20. More available for reference in attached project files.

pin assignment
pin assignment

After successfully downloading the program to the board, when you press PB 1, you should see all the LEDs are lit, after releasing, the LEDs are blinking one after the other from low to high.

 

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