FPGA Tutorial – Hexadecimal Numbers to BCD Code Conversion and Application – FPGA Board for Beginner – Experiment 7
7.1 Experiment Objective
 Convert binary numbers to BCD
 Convert hexadecimal numbers to BCD
7.2 Experiment Principle

Since the hexadecimal display is not intuitive, decimal display is more widely used in real life.

Human eyes recognition is relatively slow, so the display from hexadecimal to decimal does not need to be too fast. Generally, there are two methods
a. Countdown method:
Under the control of the synchronous clock, the hexadecimal number is decremented by 1 until it is reduced to 0. At the same time, the appropriate BCD code decimal counter is designed to increment. When the hexadecimal number is reduced to 0, the BCD counter just gets with the same value to display.
b. Bitwise operations (specifically, shift bits and plus 3 here). The implementation is as follows:


Set the maximum decimal value of the expression. Suppose you want to convert the 16digit binary value (4digit hexadecimal) to decimal. The maximum value can be expressed as 65535. First define five fourdigit binary units: ten thousand, thousand, hundred, ten, and one to accommodate calculation results

Shift the hexadecimal number by one to the left, and put the removed part into the defined variable, and judge whether the units of ten thousand, thousand, hundred, ten, and one are greater than or equal to 5, and if so, add the corresponding bit to 3 until the 16bit shift is completed, and the corresponding result is obtained.

Note: Do not add 3 when moving to the last digit, put the operation result directly


The principle of hexadecimal number to BCD number conversion. Suppose ABCD is a 4digit binary number (possibly ones, 10 or 100 bits, etc.), adjusts it to BCD code. Since the entire calculation is implemented in successive shifts, ABCDE is obtained after shifting one bit (E is from low displacement and its value is either 0 or 1). At this time, it should be judged whether the value is greater than or equal to 10. If so, the value is increased by 6 to adjust it to within 10, and the carry is shifted to the upper 4bit BCD code. Here, the premovement adjustment is used to first determine whether ABCD is greater than or equal to 5 (half of 10), and if it is greater than 5, add 3 (half of 6) and then shift. For example, ABCD = 0110 (decimal 6)

1) After shifting it becomes 1100 (12), greater than 1001 (decimal 9)
2) By plus 0110 (decimal 6), ABCD = 0010, carry position is 1, the result is expressed as decimal 12
3) Use preshift processing, ABCD = 0110 (6), greater than 5, plus 3
4) ABCD = 1001 (9), shift left by one
5) ABCD = 0010, the shifted shift is the lowest bit of the high fourbit BCD.
6) Since the shifted bit is 1, ABCD = 0010(2), the result is also 12 in decimal.
7) The two results are the same
8) Firstly, make a judgement, and then add 3 and shift. If there are multiple BCD codes at the same time, then multiple BCD numbers all must first determine whether need to add 2 and then shift.

The first way is relatively easy. Here, the second method is mainly introduced.
Example 1: Binary to BCD
Fig 7. 1 Binary to decimal
Example 2: Hexadecimal to BCD
Fig 7. 2 Hexadecimal to decimal
 Write a Verilog HDL to convert 16bit binary to BCD. (You can find reference in the project folder, HEX_BCD.v.
 ModelSim simulation


 Refer to Experiment 6 to set the simulation
 The simulation result is shown in Fig 7. 3

Fig 7. 3 Simulation for binary to decimal
 Remark
The assignment marks for the examples above are “=” instead of “<=”. Why?
Since the whole program is designed to be combinational logic, when invoking the modules, the other modules should be synchronized the timing.
7.3 Application of Hexadecimal Number to BCD Number Conversion

Continue to complete the multiplier of Experiment 6 and display the result in segment decoders in decimal. Refer to the attached project file HEX_BCD_mult.v.

Compilation. Observe the Timing Analyzer in Compilation Report.

Slow 1200mV 85C Model > Fmax Summary is 83. 71 MHz. See Fig 7. 4

Fig 7. 4 Fmax Summary

 Setup Summary
Fig 7. 5 Setup summary

 Timing Closure Recommendation. See Fig 7. 6
Fig 7. 6 Timing Analysis


From the above three indicators, the above programming does not meet the timing requirements. It can also be seen that the maximum delay path is the delay of the output of the multiplier to HEX_BCD.

There are 3 solutions:









Reduce the clock frequency

Increase the timing of HEX_BCD and increase the pipeline

Insert pipeline isolation at the periphery (can reduce some delay)








The way to increase the pipeline, will be introduced in the followup experiment, because the function of HEX_BCD is mainly used to display the humanmachine interface, the speed requirement is low, and the frequency reduction method is adopted here.
 Modify PLL to increase an output of 20 MHz frequency.
module pll_sys_rst( input inclk, output sys_clk, output BCD_clk, output reg sys_rst =1'b1 ); wire pll_locked; always@(posedge sys_clk) sys_rst <= !pll_locked; PLL PLL_inst ( .areset (1'b0), .inclk0 (inclk), .c0 (sys_clk), .c1 (BCD_clk), //20Mhz .locked (pll_locked) ); endmodule
 New code added. Refer to the project files.
reg [15:0] mult_res_r; always @ (posedge BCD_clk) mult_res_r<=mult_res;
 Recompile and observe the timing result.
 Lock the pins and download the program to FIIPRA010 board. Test it.
7.4 Experiment Summary and Reflection
 How to implement BCD using more than 16bits binary numbers
 What is a synchronous clock and how to handle an asynchronous clock
 Learn to design circuits meeting the requirement