FPGA for Beginners FPGA Tutor Pocket Boards

FPGA for Beginner Tutorial – Experiment 3 – BCD_counter – FII-PRA006

3.1 Experiment Objective

  1. Review Experiment 1, the setting for PLL, design of frequency division, and the compilation of the code

  2. Study the BCD code counter

  3. Design of 7 segment decoder

  4. Download the program into the board flash memory

3.2 Experiment Requirement

  1. The highest two segment decoders display hours, the middle two are for minutes, and the lowest two display the seconds.

  2. The decimal point will be off all the time. It will not be considered in this case.

3.3 Experiment

3.3.1 Build New Project

See Experiment 1

3.3.2 PCB Schematics

PCB-schematics-for-7-segment-decoders
PCB-schematics-for-7-segment-decoders

In Fig 3. 1, six 7 segment decoders are used in this experiment. Some points need to be paid attention.

  1. The segment names are shown above. A, B, C, D, E, F, and G correspond to the digital tube, while DP stands for the decimal point. D0, D1, D2, D3, D4, and D5 (on the rightest part) are for the current driver.

  2. They are common anode segment decoders, D0- D5 are set high or low to control the segment decoders.

  3. For the main segments, A- G are lit when the input is low, that is, ‘0’ is high.

  4. The segment decoder code is given as follows


always @ (*)
case(count_sel)
0:seven_seg_r<=7'b100_0000;
1:seven_seg_r<=7'b111_1001;
2:seven_seg_r<=7'b010_0100;
3:seven_seg_r<=7'b011_0000;
4:seven_seg_r<=7'b001_1001;
5:seven_seg_r<=7'b001_0010;
6:seven_seg_r<=7'b000_0011;
7:seven_seg_r<=7'b111_1000;
8:seven_seg_r<=7'b000_0000;
9:seven_seg_r<=7'b001_0000;
default:seven_seg_r<=7'b100_0000;
endcase
always @ (posedge sys_clk)
seven_seg<={1'b1,seven_seg_r};

5. Dynamic Scanning for human eyes. Since human eyes have visual persistence characteristics, the speed to illuminate the segment decoders is fast enough that it cannot be distinguished by naked eyes. Therefore, it can be viewed as consistent lighting instead of blinking. Like the running LED, one decoder is lit at one time, implemented in the form of low-level loop left shift

3.3.3 Experiment Procedure

  1. For the frequency division design, see Experiment 1.

  2. Dynamic scanning is implemented by the state machine. The relationship of conversion should be considered.

  3. The code implementation of one-to-one segment should be precise.

  4. Check the pin assignments before downloading the program to the board. Pin assignment file can be referred in the reference file.

3.3.4 Configuration Serial Flash Programming

Flash schematics
Flash schematics

 

In Fig 3. 2, the functionality of Flash is to save the uploaded program even after the power is turned off. If the power is on next time, the program can be running on the board immediately. It is a very useful characteristic. The specific configuration process is as follows:

  1. File > Convert Programming Files, as shown in Fig 3. 3

  2. Option setting:

  1. In Programming file type, choose JTAG Indirect Configuration File(.jic)

  2. For Configuration device, choose EPCQ 128A (compatible development board N25Q128A)

  3. In Mode, choose Active Serial

    Set jic file
    Set jic file

Fig 3. 3 Set .jic file

  1. Click Advanced and set as in Fig 3. 4

     Set the advanced option
    Set the advanced option

Fig 3. 4 Set the advanced option

  1. Click SDF Data, and then Add File, find *.sof file in the output_files. See Fig 3. 5

    Add a conversion file
    Add a conversion file

Fig 3. 5 Add a conversion file

  1. Add device. See Fig 3. 6
  2. Click Generate, and BCD_counter.jic file will be generated.

    Fig 3. 6 Add device
    Fig 3. 6 Add device

Fig 3. 6 Add device

  1. Follow the same downloading procedure in previous experiments. Observe the segment decoder on develop board.

Related posts

Leave a Comment