JTAG Configuration Description - FII-PRA010
Configuration Pocket Boards

JTAG Configuration Description – FII-PRA010 – Cyclone-10 FPGA Development Board with Jtag Embeded

FII-PRA010 – Cyclone-10 FPGA Development Board is based on our FII-PRA010 fpga board. You can buy it only $59. The official shopping website: https://fpgamarketing.com/FPGA-Study-Board-Verilog-for-beginner-Cyclone-10-FII-PRA006-FII-PRA006.htm Altera FPGA Study Board, Verilog for beginner – Cyclone-10 FPGA Development Board with Jtag Embeded – FII-PRA006 The advantage of FPGA beginner board: Beginner FPGA study board, cheaper but fully functional. cellphone sized. ( < 100 USD ) power supply and download at the same time, no extra power supply and no extra data transfer line needed Small volume and light and can be put into…

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JTAG Configuration Description - FII-PRA006
Configuration Pocket Boards

JTAG Configuration Description – FII-PRA006 – Cyclone-10 FPGA Development Board with Jtag Embeded

The latest DLL versions for Altera Quartus II or Intel Quartus Prime are 1.8b (Provided in the folder), for Quartus in Linux, get version 1.7b. To install the driver for Quartus II, do the following: Connect the MBFTDI programmer with a USB cable to a Windows computer. Make sure the device is detected and the FTDI drivers are already installed. To do this, look in the Device Manager Windows, in the COM and LPT ports section, two COM ports should appear. If instead you find two yellow question marks, then you need…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Asynchronous Serial Port Design and Experiment – FPGA for Beginner – Experiment 10

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1…

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SignalTap II simulation
FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Use Dual-port RAM to Read and Write Frame Data, use synchronous (or asynchronous ) clock to control the synchronization of frame structure – FPGA Board Beginner Tutorial – Experiment 9

Experiment 9 Use Dual_port RAM to Read and Write Frame Data 9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Experiment Implement Observing the synchronization structure of synchronous clock frames using SignalTap II Extended the use of dual-port RAM Design the use of three-stage state machine Design a 16-bit data frame Data is generated by an 8-bit counter: Data={~counta,counta} The ID of the data frame…

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Learn How to use ROM
FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Design 16 outputs ROM, Study the format of *.mif and how to edit *.mif file to configure the contents of ROM, Use of ROM (Read-only Memory) – FPGA Board for Beginner Tutorial – Experiment 8

Experiment 8 Use of ROM 8.1 Experiment Objective Study the internal memory block of FPGA Study the format of *.mif and how to edit *.mif file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Implement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment display illustrates the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Introduction to Program This experiment was carried out on the basis of Experiment 7, and…

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Hexadecimal Numbers to BCD Code(hex_to_bcd), binary numbers to BCD code (bin_to_bcd) Conversion and Application
FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Hexadecimal Numbers to BCD Code(hex_to_bcd), binary numbers to BCD code (bin_to_bcd) Conversion and Application – FPGA Board for Beginner Tutorial – Experiment 7

Experiment 7 Hexadecimal Number to BCD Code Conversion and Application Experiment Objective Learn to convert binary numbers to BCD code (bin_to_bcd) Learn to convert hexadecimal numbers to BCD code (hex_to_bcd) 7.2 Experiment Implement Combined with experiment 6, display the results of the operation to the segment display. 7.3 Experiment 7.2.1 Introduction to the Principle of Converting Hexadecimal Number to BCD Code Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eyes recognition is relatively slow, so the display from hexadecimal to decimal…

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Pipelining setting
FPGA for Beginners FPGA Tutor Pocket Boards

Learn to Use Multiplier and ModelSim to Output- FPGA Board for Beginner – FPGA Tutorial – Experiment 6

Experiment 6 Use of Multipliers and ModelSim Simulation 6.1 Experiment Objective Learn to use multiplier Use ModelSim simulation to design output 6.2 Experiment Implement 8×8 multiplier, the first input value is an 8-bit switch, and the second input value is the output of an 8-bit counter. Observe the output in ModelSim Oberseve the calculation results with a four-digit segment display 6.3 Experiment Since the simulation tools and the new IP core are used here, there is no introduction or design part of hardware. 6.3.1 Introduction of Program ModelSim is an…

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Top level design
FPGA for Beginners FPGA Tutor Pocket Boards

Block_Debouncing Principle and adaptive programming, PCB schematics, and Verilog HDL Code – FBGA Board for beginner FPGA tutorial – Experiment 5

  Experiment 5 Button Debounce Experiment 5.1 Experiment Objective Review the design process of the shifting LED Learn button debounce principle and adaptive programming Study the connection and use of the FII-PRA006/010 button hardware circuit Comprehensive application button debounce and other conforming programming 5.2 Experiment Implement Control the movement of the lit LED by pressing the button Each time the button is pressed, the lit LED moves one bit. When the left shift button is pressed, the lit LED moves to the left, presses the right button, and the lit…

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Digital clock for BDF design
FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards

Building new FPGA projects in Quartus, device selection, PLL setup, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II – FPGA Board for Beginner – Experiment 4 -PRA006

  Experiment 4 Block/SCH Experiment 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL setup, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the…

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BCD Counter Experimental
FPGA for Beginners FPGA Tutor Pocket Boards

BCD_counter, The segment decoder code, Download the program into the board flash memory – FPGA for Beginner Tutorial – Experiment 3 – FII-PRA006

  Experiment 3 Segment Display 3.1 Experiment Objective Review previous experiments, proficient practice in PLL configuration, frequency division design, and project verification; Learn to use the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower (right most) digits to display seconds, the middle two digits to display minutes, and the highest (left most) two digits to display hours. The decimal point remains off and will not be considered for the…

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