JTAG Configuration Description - FII-PRA010
Configuration Pocket Boards

JTAG Configuration Description – FII-PRA010 – Cyclone-10 FPGA Development Board with Jtag Embeded

The latest DLL versions for Altera Quartus II or Intel Quartus Prime are 1.8b (Provided in the folder), for Quartus in Linux, get version 1.7b. To install the driver for Quartus II, do the following: Connect the MBFTDI programmer with a USB cable to a Windows computer. Make sure the device is detected and the FTDI drivers are already installed. To do this, look in the Device Manager Windows, in the COM and LPT ports section, two COM ports should appear. If instead you find two yellow question marks, then you need…

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JTAG Configuration Description - FII-PRA006
Configuration Pocket Boards

JTAG Configuration Description – FII-PRA006 – Cyclone-10 FPGA Development Board with Jtag Embeded

The latest DLL versions for Altera Quartus II or Intel Quartus Prime are 1.8b (Provided in the folder), for Quartus in Linux, get version 1.7b. To install the driver for Quartus II, do the following: Connect the MBFTDI programmer with a USB cable to a Windows computer. Make sure the device is detected and the FTDI drivers are already installed. To do this, look in the Device Manager Windows, in the COM and LPT ports section, two COM ports should appear. If instead you find two yellow question marks, then you need…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Asynchronous Serial Port Design and Experiment – FPGA for Beginner – Experiment 10

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1…

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FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Use Dual-port RAM to Read and Write Frame Data – FPGA Board for Beginner – Experiment 9

9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Observing the synchronization structure of synchronous clock frames using SignalTap II Extended the use of dual-port RAM Design the use of three-stage state machine 9.2 Experiment Requirement Generate dual-port RAM and PLL 16-bit width, 256-depth dual-port RAM 2 PLL, both 50 MHz input, different 100 MHz and 20 MHz outputs Design a 16-bit data frame Data…

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FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Use of ROM (Read-only Memory) – FPGA Board for Beginner – Experiment 8

8.1 Experiment Objective Study the internal memory block of FPGA Study the format of *.mif and how to edit *.mif file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Requirement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment decoders display the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Design Procedure Build a new project named memory_rom In Installed IP, choose Library > Basic Function > On Chip Memory…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Hexadecimal Numbers to BCD Code Conversion and Application – FPGA Board for Beginner – Experiment 7

7.1 Experiment Objective Convert binary numbers to BCD Convert hexadecimal numbers to BCD 7.2 Experiment Principle Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eyes recognition is relatively slow, so the display from hexadecimal to decimal does not need to be too fast. Generally, there are two methods   a. Countdown method: Under the control of the synchronous clock, the hexadecimal number is decremented by 1 until it is reduced to 0. At the same time, the appropriate BCD code decimal…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Use Multiplier and ModelSim – FPGA Board for Beginner – Experiment 6

6.1 Experiment Objective Learn to use multiplier Use ModelSim to output 6.2 Experiment Requirement 8×8 multiplier. The first input is 8-bit switch, and the second input is the output of an 8-bit counter. Observe the output in ModelSim. Observe the calculation result on 4 segment decoders. 6.3 Experiment Build a new project mult_sim Different from what we did before, we use EDA simulation. The actual setting is shown in Fig 6. 1 Design procedure Create a new file named mult_sim.v Add PLL, set the clock input frequency is 50 MHz,…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA tutorial – Block_debouncing – FBGA Board for for beginner – Experiment 5

5.1 Experiment Objective Review the design process of running LED Learn the principle of button debounce and designing of adaptive programming Learn the connection and used of the Fii-PRA010 button Integrated application of button debounce, and furthermore development design   5.2 Experiment Bouncing button principle Usually, the switches used for the buttons are mechanical elastic switches. When the mechanical contacts are opened and closed, due to the elastic action of the mechanical contacts, a push button switch does not immediately turn on when closed, nor is it off when disconnected.…

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FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Block/ Schematic Test – FPGA Board for Beginner – Experiment 4

4.1 Experiment Objective Review the new project building, PLL setting, Verilog HDL’s tree hierarchy design, use of SignalTap Use graphics method top-down design Combine the BCD_counter design to realize the display of the digital clock Observe the experiment result 4.2 Experiment Build new project named block_counter Fig 4. 1 New file selection In Fig 4. 1, choose Block Diagram/Schematic File this time instead of Verilog HDL file. In Fig 4. 2, the middle blank part is for designing block diagram or schematics. Save the file as block_counter.bdf. Double click the…

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FPGA for Beginners FPGA Tutor Pocket Boards

FPGA for Beginner Tutorial – Experiment 3 – BCD_counter – FII-PRA006

3.1 Experiment Objective Review Experiment 1, the setting for PLL, design of frequency division, and the compilation of the code Study the BCD code counter Design of 7 segment decoder Download the program into the board flash memory 3.2 Experiment Requirement The highest two segment decoders display hours, the middle two are for minutes, and the lowest two display the seconds. The decimal point will be off all the time. It will not be considered in this case. 3.3 Experiment 3.3.1 Build New Project See Experiment 1 3.3.2 PCB Schematics…

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