2.1 Experiment Objective
- Continue to practice using the develop board
- Use SignalTap II Logic Analyzer in Quartus II
- Use FPGA configuration memory to program
2.2 Experiment Requirement
By using SignalTap II, learn to analyze and capture the experimental signals.
2.3.1 Project Building
Refer to Experiment1, the following experiment project building steps will be eliminated.
2.3.2 PCB Schematics
2.3.3 Experiment Procedure
We include the PLL1 generated in Experiment 1 Verilog HDL code is as follows:
input [7:0] sw,
output reg [7:0] led
always @(posedge inclk)
2.3.4 SignalTap II Logic Analyzer
Step 1: SignalTap II startup and basic setup
Tools > Signal Tap Logic Analyzer，
In Fig 2.2, enter the setup interface
In JTAG Chain Configuration, click setup to set the same type as the downloader
Set the scan chain type
Set the SOF Manager, choose the *.sof file generated in Experiment 1
5. Clock setting. See Fig 2. 3
6. In Fig 2. 4, in the popup window, choose SignalTap II: pre-synthesis for Filter,
in Matching Nodes column, go to PLL1: PLL_INST, select c0, and click > to move it to the right frame.
Other settings are shown in Fig 2. 2. For furthermore reference, see the attached file for help.
Step 2: Add the observation signals
In Fig 2. 2, double click any blank space to add the observation signals.
The interface is shown in Fig 2. 5, choose the signal you want to observe on the left side, click > to add them to the right side, and then click Insert.
Save it and recompile later.
Step 3: Set the observation signals
For the observation signals, some settings are still needed, such as whether it is a Rising Edge trigger, a Falling Edge trigger, or Don’t Care, etc. They need to be adjusted manually. See Fig 2. 6.
Step 4: Observe the result
In Fig 2. 7. Run the analysis and observe the SignalTap II output.
After analysis, when the switch SW  is on, the signal is high, and the corresponding LED will be lighted. You could change the trigger type and observe different outputs. Analyze the result and organize it.