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FPGA for Beginner Tutorial – Experiment 2 Switch and Use SignalTap II – FII-PRA006

2.1 Experiment Objective

  1.  Continue to practice using the develop board
  2.  Use SignalTap II Logic Analyzer in Quartus II
  3. Use FPGA configuration memory to program

2.2 Experiment Requirement

By using SignalTap II, learn to analyze and capture the experimental signals.

2.3 Experiment

2.3.1 Project Building

Refer to Experiment1, the following experiment project building steps will be eliminated.

2.3.2 PCB Schematics

switch schematics
switch schematics

2.3.3 Experiment Procedure

We include the PLL1 generated in Experiment 1 Verilog HDL code is as follows:

module SW_LED(

input inclk,
input [7:0] sw,
output reg [7:0] led

wire sys_clk;
wire pll_locked;
reg sys_rst;

always@(posedge sys_clk)

always @(posedge inclk)


.areset (1’b0),
.inclk0 (inclk),
.c0 (sys_clk),
.locked (pll_locked)



2.3.4 SignalTap II Logic Analyzer

Step 1: SignalTap II startup and basic setup

Tools > Signal Tap Logic Analyzer

        1. In Fig 2.2, enter the setup interface

        2. In JTAG Chain Configuration, click setup to set the same type as the downloader

        3. Set the scan chain type

        4. Set the SOF Manager, choose the *.sof file generated in Experiment 1

SignalTap II setup interface
SignalTap II setup interface

5. Clock setting. See Fig 2. 3


6. In Fig 2. 4, in the popup window, choose SignalTap II: pre-synthesis for Filter,

in Matching Nodes column,  go to PLL1: PLL_INST, select c0, and click > to move it to the right frame.

Clock signal selection dialog boxes
Clock signal selection dialog boxes

Other settings are shown in Fig 2. 2. For furthermore reference, see the attached file for help.

Step 2: Add the observation signals

Adding observation signal
Adding observation signal

In Fig 2. 2, double click any blank space to add the observation signals.

The interface is shown in Fig 2. 5, choose the signal you want to observe on the left side, click > to add them to the right side, and then click Insert.

Save it and recompile later.

Step 3: Set the observation signals

For the observation signals, some settings are still needed, such as whether it is a Rising Edge trigger, a Falling Edge trigger, or Don’t Care, etc. They need to be adjusted manually. See Fig 2. 6.

Setting for the trigger signal
Setting for the trigger signal

Step 4: Observe the result

In Fig 2. 7. Run the analysis and observe the SignalTap II output.

Testing result
Testing result

After analysis, when the switch SW [4] is on, the signal is high, and the corresponding LED will be lighted. You could change the trigger type and observe different outputs. Analyze the result and organize it.






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