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FPGA Tutorial – Block/ Schematic Test – FPGA Board for Beginner – Experiment 4

4.1 Experiment Objective

  1. Review the new project building, PLL setting, Verilog HDL’s tree hierarchy design, use of SignalTap

  2. Use graphics method top-down design

  3. Combine the BCD_counter design to realize the display of the digital clock

  4. Observe the experiment result

4.2 Experiment

  1. Build new project named block_counter

     New file selection
    New file selection

Fig 4. 1 New file selection

  1. In Fig 4. 1, choose Block Diagram/Schematic File this time instead of Verilog HDL file.

  2. In Fig 4. 2, the middle blank part is for designing block diagram or schematics.

    1. Save the file as block_counter.bdf.

    2. Double click the bank space to add the symbol.

       Block diagram/ schematic design interface
      Block diagram/ schematic design interface

Fig 4. 2 Block diagram/ schematic design interface

  1. In Library, find c:/, and the primitives, or just simply type the symbol name in the search box.

     Input symbols
    Input symbols

Fig 4. 3 Input symbols

  1. Add input and output and modify their names. See Fig 4. 3

  2. Add a customized symbol

    1. Add a new Block Diagram/Schematic File. Save the file as PLL_sys.bdf

    2. Create a new PLL I referring to Experiment 1.

    3. Select the new generated file to include PLL1.bsf file.

    4. Double click blank space in PLL_sys.bdf, and choose under Project, add PLL1. See Fig 4. 4

    5. Continue to add other symbols, such as input, output, dff, GND etc. Remember to modify their names. You could choose the Orthogonal node tool icon to wire them. See Fig 4. 5

      Invoke the customized symbol
      Invoke the customized symbol

Fig 4. 4 Invoke the customized symbol

 Symbol wiring
Symbol wiring

Fig 4. 5 Symbol wiring

  1. Create the symbol for the new file
    1. File > Create/ Update > Create Symbol Files for Current File. See Fig 4. 6
    2. Save as PLL_sys.bsf

      Create symbol files for current file
      Create symbol files for current file

Fig 4. 6 Create symbol files for current file

  1. Create a new Verilog HDL file for the frequency division (see reference project files)

    1. Create a new frequency divider Verilog HDL file named div_us

    2. Set PLL output clock as its own input clock. Divide the clock of 100 MHz into a clock of 1 MHz.

    3. Repeat step 7, create div_us.bsf

    4. Create a new Verilog HDL file with a frequency of 1000: div_1000f.v.

    5. Create a div_1000f.bsf symbol

  1. Create a graph of us, ms, and second output pulse files for testing. See Fig 4. 7

    1. Create a new Block Diagram/Schematic File, and add this generated symbol to block_div.bdf.

    2. Repeat step 7 and create symbol file for block_div.bdf as well.

      us, ms, second pulse
      us, ms, second pulse

Fig 4. 7 us, ms, second pulse

  1. Create a new Verilog HDL file named bcd_counter.v. Design time, minute counter and create bsf symbol. Refer Experiment 3 and implement some of the division using block_div.

  2. Combine each *.bsf and complete the design of the digital clock (block_counter.bdf). For the output, use Orthogonal Bus Tool to wire. See Fig 4. 8

     BDF designed digital clock
    BDF designed digital clock

Fig 4. 8 BDF designed digital clock

  1. Assign pins, and program it. For the board downloading, you can refer to Experiment 3.

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