FPGA Boards

Welcome to Fraser Innovation Inc. We are FPGA experts and we develop advanced FPGA development boards and Sell FPGA board online. We have a series of FPGA boards including FPGA board for beginner, AD9361 development board, RISC-V FPGA board and FPGA educational platform boards. We also provide FPGA board accessories such as Jtag. We have our own Risc-V IPCore.

FPGA Board for Beginner

FII-PRA006 – Altera FPGA Study Board, Verilog for beginner – Cyclone-10 FPGA Development Board – 

The advantage of FPGA beginner study board:

  1. Beginner FPGA study board, cheaper but fully functional. cellphone sized. ( < 100 USD )
  2. power supply and download at the same time, no extra power supply and no extra data transfer line needed
  3. Small volume and light and can be put into your pocket. size: 10cm X 7 cm.
  4. Unique function: can be a study board as well a multifunctional JTAG downloader. 
  5. We use newest version Intel FPGA within two years and you can always keep in the front of FPGA industry.

Altera FPGA Study Board Hardware Resources:

  1. seven_seg_r
  2. VGA Video Interface × 1
  3. 1G Ethernet Interface × 1
  4. I2C EEPROM × 1
  5. DIP Switch × 8
  6. Controllable  LED light × 8
  7. Photoresistance × 1
  8. Thermistor × 1
  9. Adjustable Varistor × 1
  10. Buttons × 4
  11. GPIO Interface × 2
  12. Micro usb Interface(Power Supply and downlaod ) × 1
  13. SPI Communication Interface × 1
  14. AD/DA Conversion chip × 1
  15. JTAG Download Interface × 1
  16. FLASH 32Mbit  × 1
FPGA Board for beginner with free experimental manuals
FPGA Board for beginner with free experimental manuals

 

AD9361 and AD9361 RF Transceiver™ – AD9361 Development Board

The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiver™ designed for use in 3G and 4G base station applications. Its programmability and wideband capability make it ideal for a broad range of transceiver applications. The device combines a RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor. The AD9361 receiver LO operates from 70 MHz to 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz range, covering most licensed and unlicensed bands. Channel bandwidths from less than 200 kHz to 56 MHz are supported.

AD9361 RF Agile Transceiver™ (BD9361) is a high-speed analog module designed to showcase the AD9361, a high performance, highly integrated RF transceiver intended for use in RF applications, such as 3G and 4G base station and test equipment applications, and software defined radios. Its programmability and wideband capability make it ideal for a broad range of transceiver applications.

The device combines an RF front end with a flexible mixed-signal baseband section and integrated frequency synthesizers, simplifying design-in by providing a configurable digital interface to a processor or FPGA. The AD9361 chip operates in the 70 MHz to 6 GHz range, covering most licensed and unlicensed bands. The chip supports channel bandwidths from less than 200 kHz to 56 MHz by changing sample rate, digital filters, and decimation, which are all programmable.

For More information, please check AD9361 RF Agile Transceiver™, AD9316 Development Board

AD9361 Development Board
AD9361 RF Agile Transceiver™, AD9361 Development Board

JTAG

JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture.

Processors often use JTAG to provide access to their debug/emulation functions and all FPGAs and CPLDs use JTAG to provide access to their programming functions.

JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses.

The interface connects to an on-chip test access port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts.

The JTAG standards have been extended by many semiconductor chip manufacturers with specialized variants to provide vendor-specific features.

The debug and programming tools commonly associated with JTAG only make use of one aspect of the underlying technology – the four-wire JTAG communications protocol.

Buy JTAG Buy Clicking Above link

 

RISK-V FPGA Board

FIE310G is a high performance, low power embedded real time RISV_V processor IPCoreThe main application areas aim at smart home, Wearable, sensor Fusion, IOT, and industrial control etc

Features:

  1. Fully supports the RV32IMFAC instruction architecture and provides a rich set of storage and interfaces, including: ITCM 64K(Instruction Tightly Coupled Memories) and DTCM 64K(Data Tightly Coupled Memories) for separate storage of instructions and data, and 2M bytes External super RAM support as well .
  2. 3-stage pipeline architecture
  3. support machine mode only
  4. From instruction fetch ,Decoder ,Execution to memory operation modules are 100% Manually developed by using pure verilog HDL, scalable and easy to be understood.
  5.  The flexible RISC-V IPCORE is suitable for customized ASIC for specific domain, Also can be used as embedded CPU with in FPGA.
  6.  Interrupt controller, supports 16 high-priority, low-latency local vectored interrupts.
  1. includes a RISC-V standard PLIC (platform-level interrupt controller ), which supports 127 global interrupts with 7 priority levels. provides the standard RISCV machine-mode timer and software interrupts via the CLINT(Core Local Interruptor)
  2. 2 UART
  3. 3 QSPI
  4. I2C
  5. PWM
  6. 10M/100M/1G ethernet
  7. Watchdog
  8. 32 GPIO
  9. 4 7-seg display interface
  10. External Serial Flash
  11. Debug Interfaces: JTAG
  12. 12-Bit ADC
  13. Four data lines I2S and can support maximum of 8 audio outputs or 4 stereo channels
  14. Hardware Crypto Engine for Advanced Fast Security, Including: AES 128, CRC, Checksum etc

 

Risc-V Development Board
Risc-V Development Board
  1. Suitable for FPGA study and training
  2. Fully support FIE310 CPU running and system development
  3. Suitable for user customized RV32G verification and validation
  4. JTAG interface for FPGA and FIE310 CPU download and debug
  5. Support Windows software and linux development environment
  6. GCC compilation toolchain and graphical software development environment
  7. Hardware resource:   Switchs, Push Button ,USB to UART convertorQSPI flashI2C EEPROM, 100M/1G ethernet, USB keyboard mouse,GPIO hdmi transmitter and camera etc.

 

 

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