Risc-V

1.Introduction to FII-RISCV CPU Direct to Table of Contents: RISC-V Syllabus First of all, there is an overview of the CPU, FII-RISCV. RISCV is an open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles [1]. FII-RISCV is researched and developed following the RISCV standard. Here are some basic features about FII-RISCV: RV32I (32 registers that supports integer operations) Does not support multiplication instructions (the newest version do support) Does not support Atomic operations Does not support compressed instruction Supports software interrupt Supports…

FII RISC-V3.01 CPU FII-PRA040 FII-PRX100-S FII-PRX100D Risc-V Risc-V Core Risc-V Tutorial

RISC-V Instruction Set Explanation

December 1, 2020May 17, 2021 beginner FPGAAddress alignment, B-type, General-Purpose Register, Handle overflow situations, I-type, Instruction Set, J-type, Load & Store, R-type, Risc-V, RISC-V base instruction formats, RISC-V base instruction formats 6, U-type

V1.0 Fraser Innovation inc RISCV instruction set explanation Version Control Version Date Description V1.0 2020/11/27 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how to use the product correctly. Improper…

FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

Risc-V Bus and PipeLine – FII Risc-V Bus and Pipeline Design – Risc-V Tutorial and Exercise

November 9, 2020November 9, 2020 beginner FPGABus, FII Risc-V Bus and Pipeline Design, PipeLine, Risc-V, Risc-V Exercise, Risc-V Tutorial

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board Bus and Pipeline Version Control Version Date Description 1.0 10/28/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D FPGA Board Based PRX100 Risc-V Core Risc-V Tutorial

FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Porting Guide

October 8, 2020February 1, 2021 SteveGuysCoremark Porting, CPU Processor, FII-PRX100-S, Risc-V, RISC-V3.01, XILINX FPGA Board

V1.1 Fraser Innovation inc FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Porting Guide Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/06/2020 Add Comparison Figure and Full Description of PRX100 Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual…

Altera RISC-V SoC AI FII-PRA040 FPGA development Board

Experimental Manuals FII-PRA040

Atera Risc-V FII-PRA040 Experimental Manuals ( 1- 20 ) PDF Version 2019-12-30

September 30, 2020 SteveGuysAtera, Experimental Manuals, FII-PRA040, Risc-V

Atera Risc-V FII-PRA040 Experimental Manuals ( 1- 20 ) PDF Version 2019-12-30 Version

Experimental Manuals FPGA Tutor PRX100 Risc-V

Understand the register configuration of the ADV7511, HDMI Graphic Display Experiment – Xilinx Risc-V Board Tutorial : FII-PRX100 FPGA Board Experiment 14

July 29, 2019August 6, 2020 SteveGuysADV7511, HDMI Graphic Display, Prx100, Risc-V, Xilinx

Experiment 14 HDMI Graphic Display Experiment 1.Experiment Objective Learn about video timing (2) Understand the register configuration of the ADV7511, reviewing the knowledge from experiment 12 2.Experiment Requirement Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. Display the image using the HDMI interface of the development board. Download the program to the board for comparison. Introduction to HDMI:…

Experimental Manuals FPGA Tutor PRX100 Risc-V

digital-to-analog conversion: DAC, analog-to-digital conversion: ADC – Xilinx Risc-V Board Tutorial : AD, DA Experiment – FII-PRX100 FPGA Board Experiment 13

July 29, 2019July 31, 2020 SteveGuysAD, DA Experiment, PCF8591, Prx100, Risc-V, Xilinx

Experiment 13 AD, DA Experiment 1.Experiment Objective Since in the real world, all naturally occurring signals are analog signals, and all that are read and processed in actual engineering are digital signals. There is a process of mutual conversion between natural and industrial signals (digital-to-analog conversion: DAC, analog-to-digital conversion: ADC). The purpose of this experiment is twofold: Learning the theory of AD conversion Read the value of AD acquisition from PCF8591, and convert the value obtained into actual value, display it with segment decoders 2.Experiment Requirement Perform analog-to-digital conversion using…

Experimental Manuals FPGA Tutor PRX100 Risc-V

Learning the basic principles of the different IIC bus, mastering the IIC communication protocol, Xilinx Risc-V Board Tutorial : IIC Protocol Transmission – FII-PRX100 FPGA Board Experiment 12

July 29, 2019January 29, 2021 SteveGuysIIC Protocol Transmission, PTX100, Risc-V, SDA

Experiment 12 IIC Protocol Transmission 1.Experiment Objective There is an IIC interface EEPROM chip 24LC02 in the test plate, capacity sized 2 kbit (256 bite). Since the data is not lost after the EEPROM is powered down, users can store some hardware setup data or user information. Learning the basic principles of the different IIC bus, mastering the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 2.Experiment Requirement Correctly write a number to any address in the EEPROM (this experiment writes to…

ModelSim simulation waves sent by serial

Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Asynchronous Serial Port Design and Experiment – FII-PRX100 FPGA Board Experiment 11

July 29, 2019February 9, 2020 SteveGuysAsynchronous Serial Port Design, Prx100, Risc-V

Experiment 11 Asynchronous Serial Port Design and Experiment 1.Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 2.Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start bit,…

Risc-V Board - Dual_port RAM test result

Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Use Dual_port RAM to Read and Write Frame Data – FII-PRX100 FPGA Board Experiment 10

July 29, 2019January 11, 2020 SteveGuysPrx100, Risc-V

Experiment 10 Use Dual_port RAM to Read and Write Frame Data 1.Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Observing the synchronization structure of synchronous clock frames using ILA Extended the use of dual-port RAM Design the use of three-stage state machine 2.Experiment Requirement Generate dual-port RAM and PLL 16-bit width, 256-depth dual-port RAM 2 PLL, both 50 MHz input, different 100 MHz and 20…