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xilinx Risc-V FPGA Board – FII-PRX100 – Development System Introduction

 

FII-PRX100 Development Board ( ARTIX 100T, XC7A100T, RISC-V FPGA Developing Board)

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https://fpgamarketing.com/FII-PRX100-ARTIX-100T-XC7A100T-RISC-V-FPGA-Board-PRX100-1.htm

  1. System Design Objective

The main purpose of this system design is to complete FPGA learning, development and experiment with Xilin-Vivado. The main device uses the Xilinx-XC7A100T-2FGG676I and is currently the latest generation of FPGA devices from Xilinx. The main learning and development projects can be completed as follows:

  1. Basic FPGA design training
  2. Construction and training of the SOPC (Microblaze) system
  3. IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU
  4. Development and application based on RISC-V
  5. The system is specifically optimized for hardware design for RISC-V system applications

2. System Resource

  1. Extended memory
  2. Use two Super Srams in parallel to form a 32-bit data interface with a maximum access space of 2M bytes.
  3. IS61WV51216 (2 pieces) 512K x 32bit
  4. Serial flash
  5. Spi interface serial flash (128M bytes)
  6. Serial EEPROM
  7. Gigabit Ethernet: 100/1000 Mbps
  8. USB to serial interface: USB-UART bridge

 

3. Human-computer Interaction Interface

  1. 8 toggle switches
  2. 8 push buttons
  3. Definition of 7 push buttons: up, down, left, right, ok, menu, return
  4. 1 for rest: Reset button
  5. 8 LEDs
  6. 6 7-segment decoders
  7. I2C bus interface
  8. UART external interface
    1. Two JTAG programming interfaces
  9. One is for downloading the FPGA debug interface, and the other one is the JTAG debug interface for the RISC-V CPU
  10. Built-in RISC-V
  11. CPU software debugger, no external RISC-V JTAG emulator required
    1. 12-pin GIPIO connectors, in line with PMOD interface standards

 

Software Development System

  1. Vivado 18.1 and later version for FPGA development, Microblaze SOPC
  2. Freedom Studio-Win_x86_64 Software development for RISC-V CPU

5.  Supporting Resources

    1. RISC-V  JTAG Debugger
    2. xilinx Altera JTAG Download Debugger
    3. FII-PRX100 Development Guide

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