Atera Risc-V Segment Display Experimental
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Altera Risc-V FPGA Tutorial : Segment Display – FII-PRA040 FPGA Board Experimental 3

Experiment 3 Segment Display

3.1 Experiment Objective

  1. Review experiment 1, proficient in PLL configuration, frequency division design, and project verification;
  2. Learn the BCD code counter;
  3. Digital display decoding design;
  4. Learn to download the project into the serial FLASH of the development board;

3.2 Experiment Implement

  1. The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours.
  2. The decimal point remains off and will not be considered for the time being.

3.3 Experiment

3.3.1 Introduction to the Segment Display

One type of segment display is a semiconductor light-emitting device. The segment display can be divided into a seven-segment display and an eight-segment display The difference is that the eight-segment display has one more unit for displaying the decimal point, the basic unit is a light-emitting diode. The on-board segment display is a six-in-one eight-segment display as shown in Figure 3.1, and its structure is shown in Figure 3.2.

Figure 3.1 Segment display physcial picture

Figure 3.2 Single segment display structure

Common anode segment display are used here. That is, the anodes of the LEDs are connected. See Figure 3.3. Therefore, the FPGA is required to control the cathode of the LED to be low level, illuminate the diode, and display the corresponding information. The six-digit common anode eight-segment display refers to the signal that controls which one is lit, which is called the bit selection signal. The content displayed by each digital segment is called the segment selection signal. The corresponding truth table is shown in Table 3.1.

Figure 3.3 Schematics of common anode LEDs

Table 3.1 8-segment display truth table

Signal Segment DP G F E D C B A
· 0 1 1 1 1 1 1 1
0 1 1 0 0 0 0 0 0
1 1 1 1 1 1 0 0 1
2 1 0 1 0 0 1 0 0
3 1 0 1 1 0 0 0 0
4 1 0 0 1 1 0 0 1
5 1 0 0 1 0 0 1 0
6 1 0 0 0 0 0 1 0
7 1 1 1 1 1 0 0 0
8 1 0 0 0 0 0 0 0
9 1 0 0 1 0 0 0 0
A 1 0 0 0 1 0 0 0
B 1 0 0 0 0 0 1 1
C 1 1 0 0 0 1 1 0
D 1 0 1 0 0 0 0 1
E 1 0 0 0 0 1 1 0
F 1 0 0 0 1 1 1 0

There are two ways to display the segment display, static display and dynamic display.

Static display: Each display segment is connected with an 8-bit data line to control and maintain the displayed glyph until the next segment selection signal arrives. The advantage is that the driver is simple, and the disadvantage is that it takes up too much I/O resources.

Dynamic display: Parallel the segment selection lines of all segment display, and the digit selection line controls which digit is valid and lights up. Through the afterglow effect of the LED and the persistence effect of the human eye, the segment display appears to be continuously lit at a certain frequency. The advantage is to save I / O resources, the disadvantage is that the driver is more complicated, the brightness is not static display high.

In this experiment, the digital tube was driven by dynamic scanning.

3.3.2 Hardware Design

The schematics of the digital tube is shown in Figure 3.4. The anode is connected to VCC through the P-channel field corresponding tube. Therefore, when the bit selection signal SEG_3V3_D[0:5] is low level 0, the FET is turned on, the anode of the segment display is high level; the cathode (segment selection signal) SEG_PA, SEG_PB, SEG_PC, SEG_PD, SEG_PE, SEG_PF, SEG_PG, SEG_DPZ are directly connected to the FPGA and directly controlled by the FPGA. Therefore, when the bit selection signal is 0, and the segment selection signal is also 0, the segment display is lit.

Figure 3.4 Schematics of the segment display

3.3.3 Program Design

3.3.3.1 Introduction of the Program

The first step: the establishment of the main program framework (interface design)

module BCD_counter (

input clk,

input rst_n,

output [7:0] seven_seg,

output [5:0] scan

);

endmodule

The input signal has a clock and a reset signal, and the output signal is a segment selection signal seven_seg and a new signal scan.

Step 2: System Control Module

//Instantiate PLL

PLL PLL_inst

(

.areset (1’b0),

.inclk0 (clk),

.c0 (sys_clk),

.locked (locked)

);

//Reset signal

always @ (posedge sys_clk)

begin

sys_rst <= !locked;

ext_rst <= rst_n;

end

In the first sub-module (system control module), the input clock is the system 50 MHz clock, and a 100MHz is output through the phase-locked loop as the working clock of the other sub-modules. The phase-locked loop lock signal is inverted as the system reset signal. The button is reset to be used as an external hardware reset signal.

The third step: the frequency division module

Referring to Experiment 1, a millisecond pulse signal and a second pulse signal are output as input signals of the segment display driving module.

The fourth step: segment display driver module

  1. Counting section

The counting part is similar to the frequency dividing module. It is timed by the second pulse signal for 60 seconds, 60 minutes, 24 hours, and when the time reaches 23 hours, 59 minutes and 59 seconds, the counters are all cleared, which is equivalent to one day.

  1. Segment display dynamic scanning part
reg [3:0] count_sel;

reg [2:0] scan_state;

always @ (posedge clk)

begin

if (rst) begin

scan <= 6’b111_111;

count_sel <= 4’d0;

scan_state <= 0;

end

else case (scan_state)

0 :

begin

scan <= 6’b111_110;

count_sel <= counta;

if (ms_f)

scan_state <= 1;

end

1 :

begin

scan <= 6’b111_101;

count_sel <= countb;

if (ms_f)

scan_state <= 2;

end

2 :

begin

scan <= 6’b111_011;

count_sel <= countc;

if (ms_f)

scan_state <= 3;

end

3 :

begin

scan <= 6’b110_111;

count_sel <= countd;

if (ms_f)

scan_state <= 4;

end

4 :

begin

scan <= 6’b101_111;

count_sel <= counte;

if (ms_f)

scan_state <= 5;

end

5 :

begin

scan <= 6’b011_111;

count_sel <= countf;

if (ms_f)

scan_state <= 0;

end

default : scan_state <= 0;

endcase

end

The dynamic scanning of the segment display is realized by the state machine. A total of six segment display require six states. The state machine scan_state[2:0] is defined, and the corresponding content count_sel is displayed in different states. At reset, all six segment display are extinguished and jump to the 0 state. The segment display is dynamically scanned in 1 millisecond time driven by a millisecond pulse:

In the 0 state, the 0 segment display is lit, and the ones digit of the second is displayed;

In the 1 state, the first segment display is lit, and the tens digit of the second is displayed;

In the 2 state, the second segment display is lit, and the ones digit of the minute is displayed;

In the 3 state, the third segment display is lit, and the tens digit of the minute is displayed;

In the 4 state, the fourth segment display is lit, and the ones digit of the hour is displayed;

In the 5 state, the fifth segment display is lit, and the tens digit of the hour is displayed;

Part 5: segment code display section

always @ (*)

begin

case (count_sel)

0 : seven_seg_r <= 7’b100_0000;

1 : seven_seg_r <= 7’b111_1001;

2 : seven_seg_r <= 7’b010_0100;

3 : seven_seg_r <= 7’b011_0000;

4 : seven_seg_r <= 7’b001_1001;

5 : seven_seg_r <= 7’b001_0010;

6 : seven_seg_r <= 7’b000_0010;

7 : seven_seg_r <= 7’b111_1000;

8 : seven_seg_r <= 7’b000_0000;

9 : seven_seg_r <= 7’b001_0000;

default : seven_seg_r <= 7’b100_0000;

endcase

end

Referring to Table 3.1, the characters to be displayed are associated with the segment code, the decimal point is set high, and then the final output segment selection signal is composed in a spliced form.

3.4 Flash Application and Experimental Verification

The first step: pin assignment

Pin assignments are shown in Table 3.1.

Table 3.1 Segment display pin mapping

Signal Name Network Label FPGA Pin Port Description
clk CLK_50M G21 Input clock
rst_n PB3 Y6 reset
scan[0] SEG_3V3_D0 F14 Bit selection 0
scan[1] SEG_3V3_D1 D19 Bit selection 1
scan[2] SEG_3V3_D2 E15 Bit selection 2
scan[2] SEG_3V3_D2 E13 Bit selection 3
scan[4] SEG_3V3_D4 F11 Bit selection 4
scan[5] SEG_3V3_D5 E12 Bit selection 5
seven_seg[0] SEG_PA B15 Segment a
seven_seg[1] SEG_PB E14 Segment b
seven_seg[2] SEG_PC D15 Segment c
seven_seg[3] SEG_PD C15 Segment d
seven_seg[4] SEG_PE F13 Segment e
seven_seg[5] SEG_PF E11 Segment f
seven_seg[6] SEG_PG B16 Segment g
seven_seg[7] SEG_DP A16 Segment h

The second step: compilation

The third step: solidify the program to Flash

Onboard Flash (N25Q128A) is a serial Flash chip that can store 128Mbit of content, which is more than enough for the engineering process in the learning process. The schematics of the Flash is shown in Figure 3.7.

Figure 3.7 Schematics of FLASH

The function of Flash is to save the program on the development board. After the power is off, the program will not disappear. The next time the development board is powered on, it can be used directly. It is more practical in the actual learning life. Driven by the SPI_CLK clock, the FPGA downloads the program to Flash through the SPI_ASDO line. After power-on, the FPGA re-reads the program to the FPGA through SPI_XDATA for testing.

The specific configuration process of Flash is as follows:

  1. Menu File -> Convert programming files, as shown in Figure 3.8;
  2. Option settings
  3. Select JTAG Indirect configuration File(*.Jic)
  4. Configuration Device: EPCQ 128A (Compatible with development board N25Q128A)
  5. Mode:Active serial

Figure 3.8 *.jic file setting

  1. Click the Advanced button and set it as shown in Figure 3.9.

Figure 3.9 Advanced option setting

  1. Add a conversion file, as shown in Figure 3.10.

Figure 3.10 Add conversion file

  1. Add a device, as shown in Figure 3.11.

Figure 3.11 Add devices

  1. Click Generate to generate the BCD_counter.jic file
  2. Consistent with previous program verification operations, select the correct file (*.jic) to download

The fourth step: power up verification

shown in Figure 3.12, after power-on, the FPGA automatically reads the program in Flash into the FPGA and runs it.

Atera Risc-V Segment Display Experimental Results
Atera Risc-V Segment Display Experimental Results

Figure 3.12 Experiment result

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