Experimental Manuals FPGA Tutor Risc-V

Use multiplier, Use ModelSim to simulate design output, Use of Multipliers and ModelSim – FII-PRA040 Altera Risc-V FPGA Board Experimental 6

Experiment 6 Use of Multipliers and ModelSim

6.1 Experiment Objective

  1. Learn to use multiplier
  2. Use ModelSim to simulate design output

6.2 Experiment Implement

  1. 8×8 multiplier, the first input value is an 8-bit switch, and the second input value is the output of an 8-bit counter.
  2. Observe the output in ModelSim
  3. Observe the calculation results with a four-digit segment display

6.3 Experiment

Since learning uses of the simulation tools and the new IP core, there is no introduction and hardware design part.

6.3.1 Introduction of Program

ModelSim is an HDL language simulation software. Our program can be simulated to achieve inspection and error correction. ModelSim, different from the previous experiment, when building the project, you need to add the simulation tool to be used in the EDA tool selection window. See Figure 6.1.

EDA Tool Setting

Only one counter, one PLL and one multiplier are used in the program. Only the multiplier is introduced here.

The first step: the establishment of the main program framework

module mult_sim (

input inclk,

input rst,

input [7:0] sw,

output [15:0] mult_res,

output reg [7:0] count


The value of the switch is used as the first input of the multiplier, the value of the counter is the second input, and the result of the calculation is output.

Step 2: The multiplier IP core setting steps are as follows:

  1. After adding the LPM_MULT IP (IP Catalog -> Library -> Basic Functions -> Arithmatic -> LPM_MULT) and saving the path, the setting window of the multiplier is popped up, as shown in Figure 6.2, and the two input data is set to eight bits as required.

Figure 6.2 mult setting 1

  1. Select the multiplication type to be Unsigned. See Figure 6.3.

Figure 6.3 mult setting 2

  1. Select the pipeline to speed up the operation, as shown in Figure 6.4.
  2. Select others to be default

Figure 6.4 mult setting 3

8×8 multiplier instantiation:

reg sys_clk;

mult_8x8 mult_8x8_inst (

.clock (sys_clk),

.dataa (sw),

.datab (count),

.result (mult_res)


6.4 Use of ModelSim and the Experiment Verification

Here, use ModelSim to simulate verifing the experiment.

Method 1: Simulation based on waveform input

  1. Click the menu bar Tools -> Options, as shown in Figure 6.5, click OK.

Figure 6.5 Set Modelsim-Altera path

  1. Tool -> Run Simulation Tool -> RTL Simulation. See Figure 6.6.

Figure 6.6 ModelSim interface

  1. Set ModelSim
  2. Simulate -> Start Simulation
  3. In the popup window, add libraries under Libraries tag. See Figure 6.7.

Figure 6.7 Add simulation libraries

  1. Under Design tag, choose simulation project mult_sim and click OK. See Figure 6.8.

Figure 6.8 Choose the project in simulation

  1. In the Objects window, choose all the signals and drag them to Wave window. See Figure 6.9.

Figure 6.9 Add observation signals

  1. Set the signals in Wave, right click any signal and a selection window will occur. See Figure 6.10.

Figure 6.10 Set the signals

  1. logical signals select Force and select Clock for clock signals
  2. Set rst signal. See Figure 6.11.

Figure 6.11 Set rst signal

  1. Set Inclk signal. See Figure 6.12.

Figure 6.12 Set inclk signal

  1. Set sw signal. See Figure 6.13.

Figure 6.13 Set sw signal

  1. Run simulation. In the tool bar, set the simulation time to be 100 ns. Click the Run icon to run. See Figure 6.14.

Figure 6.14 Set the simulation time

  1. Observe the simulation result. See Figure 6.15.

Figure 6.15 Simulation result

  1. Result analysis
  2. Counter count does not have a valid result, instead, unknow result XXXXXX is gotten.
  3. sys_rst does not reset signals. It changes from X to 0
  4. Add pll_locked signal to the wave, and re-simulate
  5. In Figure 6.16, before PLL starts to lock, the sys_clk already has a rising edge, so PLL_locked signal is just converted from low to high. There is no reliable reset is formed.

Figure 6.16 Re-simulation result

  1. Solution
  2. Define sys_rst to be 1’b0
  3. Use external rst signal to procide reset

Here method a is adopted. The revised code is as follows:

module pll_sys_rst(

input inclk,

output sys_clk,

output reg sys_rst = 1’b1


  1. Recompile the simulation.

Figure 6.17 Recompile the simulation

Since waveform editing efficiency is relatively low, the use of simulation testbench file is encouraged.

Method 2: Write a testbench file for simulation

  1. Name a new Verilog HDL file tb_mult.v.
  2. The code is as follows:
`timescale 1ns/1ps

module tb_mult;

reg rst;

reg clk;

reg [7:0] sw;

wire [7:0] count;

wire [15:0] mult_res;

// S1 is the instance of simulation module

mult_sim S1(

.rst (rst),

.inclk (clk),

.sw (sw),

.count (count),

.mult_res (mult_res)


// Define the clock required for the simulation and display the results in text form

always begin

#10 clk = ~clk;

$monitor (“%d * %d = %d”, count, sw, mult_res);


//Set the simulation

initial begin

rst = 0;

clk = 1;


#10 sw = 20;

#10 sw = 50;

#10 sw = 100;

#10 sw = 101;

#10 sw = 102;

#10 sw = 103;

#10 sw = 104;

#50 sw = 105;

//stop signal

#1000 $stop;



When writing the testbench file, first mark the time unit of the simulation at the beginning, this experiment is 1 ns, then instantiate the project that needs to be simulated into the testbench file, define the clock cycle and the simulation conditions, and stop the simulation after a certain time. This simulation stops after 1000 clock cycles.

After the compilation, the testbench file is added to the ModelSim for simulation, the specific steps are as follows:

  1. Set the testbench file: Assignments -> Settings. See Figure 6.18.

Figure 6.18 Simulation setting 1

  1. In Compile test bench, click Test Benches to add tb simulation file. See Figure 6.19.

Figure 6.19 Simulation setting 2

  1. Click New, input the Test bench name. Make the name be consistent with tb file. See Figure 6. 20.

Figure 6.20 Simulation setting 3

  1. the red ellipse to add the test bench file. Find tb_mult.v file written before.
  2. Click Add to add. Click OK (three times) to finish the setting. See Figure 6.21.

Figure 6.21 Simulation setting 4

  1. Repeat previous step, to start ModelSim to simulate. See Figure 6.22.

Figure 6.22 Waveform output

After a certain delay, outputs will display in Transcript. See Figure 6.23

Because the result of the operation will be one clock cycle later than the input, the multiplier and the result will differ by one line, which does not seem to match, but does not affect the analysis of the experimental results.

Figure 6.23 Text displays operation result

Summary and Reflection

Try to use the switch as the input to the multiplier. The upper four digits are one number, the lower fourth digit is a number, and the two numbers are multiplied to output the result.

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