FII-PRA040 - Part 2

OV5640 Camera Photo Display Experiment, IIC bus, HDMI, Understand the power-on sequence of the OV5640 – FII-PRA040 Altera Risc-V Experiment 17

September 30, 2020February 1, 2021 SteveGuys5640 power-on sequence, HDMI, IIC bus, OV5640 Camera, OV5640 Camera Photo Display Experiment, OV5640 datasheet, register configuration process

Experiment 17 Photo Display Experiment of OV5640 Camera 17.1 Experiment Objective Understand the power-on sequence of the OV5640 camera and the corresponding register configuration process when outputting images of different resolutions Review previous knowledge of IIC bus Review previous knowledge of HDMI 17.2 Experiment Implement Read the power-on sequence of the OV5640 datasheet, and correctly write the power-on control program according to the peripheral module schematics. Correctly write the configuration program of the OV5640 camera with a resolution of 640X480 according to the timing requirements of the SCCB interface Based…

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Audio 8978 Loopback Experiment (WM8978 Audio Sub Development Board) , How I2S (Inter-IC Sound) bus work ? – – FII-PRA040 Altera Risc-V Tutorial Experiment 16

September 30, 2020September 30, 2020 SteveGuysAudio Bus Protocol, Audio Loopback Experiment, Control Interface Timing, I2S protocol, Inter-IC Sound Bus, MODE pin, WM8978, wm8978 board verification

Experiment 16 8978 Audio Loopback Experiment 16.1 Experiment Objective Learn about I2S (Inter-IC Sound) bus and how it works Familiar with the working mode of WM8978. And by configuring the interface mode and selecting the relevant registers in combination with the development board, complete the data transmission and reception, and verify it 16.2 Experiment Implement Perform audio loopback test by configuring the onboard audio chip WM8978 to check if the hardware is working properly Adjust the volume output level with the keys. 16.3 Experiment 16.3.1 WM8978 Introduction WM8978 is a…

FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

How does SRAM read and write work ? Review frequency division, button debounce, and hex conversion experiment – FII-PRA040 Altera Risc-V Tutorial Experiment 15

September 30, 2020September 30, 2020 SteveGuysButton Debounce, frequency division, hex conversion, How does SRAM read and write, pin assignment, Schematics of SRAM, SRAM read and write

Experiment 15 SRAM Read and Write 15.1 Experiment Objective Learn the read and write of SRAM Review frequency division, button debounce, and hex conversion experiment content 15.2 Experiment Implement Control the read and write function of SRAM by controlling the button The data written to the SRAM is read out again and displayed on the segment display In the process of reading data, it is required to have a certain time interval for each read operation. 15.3 Experiment 15.3.1 Introduction to SRAM SRAM (Static Random-Access Memory) is a type of…

FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

How does Ethernet work? MII, GMII, RGMII interface advantages and disadvantages, Perform a loopback test, FII-PRA040 Altera Risc-V Tutorial Experiment 14

September 30, 2020September 30, 2020 SteveGuysGMII interface, How does Ethernet work, Loopback test design, MII interface, RGMII interface, RGMIIRGMII, RTL8211E-VB

Experiment 14 Ethernet 14.1 Experiment Objective Understand what Ethernet is and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (FII-PRA040 uses RGMII) Combine the development board to complete the transmission and reception of data and verify it 14.2 Experiment Implement Perform a loopback test to check if the hardware is working properly. Perform data receiving verification Perform data transmission verification 14.3 Experiment 14.3.1 Introduction to Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method…

HDMI interface and ADV7511 chip physical photo

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Learn HDMI principle, Introduction to HDMI and ADV7511 Chip, HDMI Display, FII-PRA040 Altera Risc-V tutorial Experiment 13

September 30, 2020September 30, 2020 SteveGuysADV7511 Chip, ADV7511 Hardware Users Guide, ADV7511 Programming Guide, HDMI, IIC bus, IIC protocol, Schematics of HDMI, Vertical synchronization

Experiment 13 HDMI Display 13.1 Experiment Objective Review IIC protocol Review EEPROM read and write Learn HDMI principle 13.2 Experiment Implement Display different image content on the screen through the HDMI. 13.3 Experiment 13.3.1 Introduction to HDMI and ADV7511 Chip Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. HDMI (High Definition Multimedia Interface) is a digital video/audio interface…

FII-PRA040

FII-PRA040 User Experimental Manuals ( 2020-09-28 Updated )

September 28, 2020September 30, 2020 SteveGuysAudio Bus Protocol, WM8978 Control Interface Timing

PRA040 USER EXPERIMENTAL MANUAL PRA040 EXPERIMENTAL INSTRUCTIONS FRASER INNOVATION INC December 07, 2019 Version Control Version Date Description 1.0 07/20/2019 Initial Release 1.1 07/29/2019 Add Experiment 15 1.2 07/31/2019 Revised some description about HDMI 1.3 08/16/2019 SRAM part revised 1.4 08/30/2019 Add a description in Ethernet 1.5 09/17/2019 Revise some syntax and code error 1.6 12/06/2019 Add Experiments 16-19 Contents Project Files Appendix 9 Part One: Introduction of FII-PRA040 Development System 10 1、Design Objective of the System 10 2、System Resource 10 3、Human-computer Interaction Interface 10 4、Software Development System 11…

Experimental Manuals FII-PRA040 FPGA Tutor Risc-V

The design process of the shifting LED, debounce principle and adaptive programming, button hardware circuit, Button Debounce Programming – FII-PRA040 Risc-V FPGA Board Experimental 5

August 8, 2019August 11, 2020 SteveGuysButton Debounce Programming, button hardware circuit, debounce principle and adaptive programming, The design process of the shifting LED

Experiment 5 Button Debounce 5.1 Experiment Objective Review the design process of the shifting LED Learn button debounce principle and adaptive programming the connection and use of the Fii-PRA040 button hardware circuit Comprehensive application button debounce and other conforming programming 5.2 Experiment Implement Control the movement of the lit LED by pressing the button Each time the button is pressed, the lit LED moves one bit. When the left shift button is pressed, the water lamp moves to the left, presses the right button, and the water lamp moves to…

Experimental Manuals FII-PRA040 FII-PRX100-S FII-PRX100D FPGA Tutor Risc-V

use Quartus II to create projects，FPGA pin assignment， program downloading， writing of Verilog HDL programs， Altera Risc-V FPGA Tutorial : LED shifting – FII-PRA040 FPGA Board Experimental 1

August 8, 2019August 5, 2020 SteveGuysLED physical picture, Quartus, The schematics of LED, Verilog HDL

Experiment 1 LED shifting 1.1 Experiment Objective Practice to use Quartus II to create new projects and use system resources IP Core; Proficiency in the writing of Verilog HDL programs to develop a good code writing style; Master the design of the frequency divider to implemnet the runing LED; Combine hardware resources to perform FPGA pin assignment and implement actual program downloading; Observe the experiment result and summarize it. 1.2 Experiment Implement Use all LEDS, all light up during reset; End reset, LED lights from low to high (from right…

Experimental Manuals FII-PRA040 FPGA Board Based Risc-V

SOPC (NiosII) system, simulation and verification of RISC-V CPU, Basic FPGA design training, IC design and verification – Altera Risc-V Board Tutorial : Introduction of FII-PRA040 Development System

August 3, 2019August 11, 2020 SteveGuysBasic FPGA design training, FPGA design training, hardware design for RISC-V system applications, IC design and verification, RISC-V CPU, SOPC (NiosII) system

1、Design Objective of the System The main purpose of this system design is to complete FPGA learning, development and experiment with Intel Quartus. The main device uses the Inte Cyclone10 10CL040YF484C8G and is currently the latest generation of FPGA devices from Intel. The major learning and development projects can be completed as follows: Basic FPGA design training Construction and training of the SOPC (NiosII) system IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU Development and application based on RISC-V The system is specifically…