FII-BD9371 FPGA Board Based RF Transceivers


ADRV9371-W/PCBZ Compatible RF/IF and RFID FPGA Board -$999 – AD9371 Development Board- FII-BD9371 Board  AD9371 Evaluation Boards AD9371 Overview The AD9371 RF transceiver is designed for applications that require high performance radio transmissions across a wideband frequency range, such as 3G/4G Macro BTS, 3G/4G Massive MIMO, and SDR. The AD9371 is packaged in a highly integrated 12mm x 12mm SoC which replaces as many as 20 high performance discrete components. Introducing the AD9371 The AD9371 RF transceiver is for applications that require high performance radios across a wideband frequency range…

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FII RISC-V3.01 CPU FII-PRA040 FII-PRX100-S FII-PRX100D Risc-V Risc-V Core Risc-V Tutorial

RISC-V Instruction Set Explanation

V1.0 Fraser Innovation inc RISCV instruction set explanation Version Control Version Date Description V1.0 2020/11/27 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how to use the product correctly. Improper…

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Graphic Design Interface
Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Combined With the BCD_Counter Project to Achieve the Display of the Digital Clock, Master the Design Method of Graphics From Top to Bottom – Block/SCH – Altera Risc-V Board PRA040 Experimental 4

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3…

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Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V Risc-V Core

Frequency Division Design, Learn the BCD Code Counter, Digital Display Decoding Design, Segment Display – Altera Risc-V Board PRA040 Experimental 3

Experiment 3 Segment Display 3.1 Experiment Objective Review experiment 1, proficient in PLL configuration, frequency division design, and project verification; Learn the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. The decimal point remains off and will not be considered for the time being. 3.3 Experiment 3.3.1 Introduction to the…

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FII RISC-V3.01 CPU FII-PRA040 Risc-V Risc-V Core

Learn to Analyze the Captured Signals, Practice the Use of SignalTap Logic Analyzer in Quartus – SignalTap – Altera Risc-V Board PRA040 Experimental 2

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice the use of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Use switches to control the LED light on and off Capture and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction of DIP Switches and SignalTap Introduction of switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the…

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Experimental Manuals FII RISC-V3.01 CPU FII-PRA040 FPGA Tutor Risc-V Risc-V Core

Master the Design of the Frequency Divider to Implement the Shifting – LED LED Shifting – Altera Risc-V Board PRA040 Experimental 1

Experiment 1 LED shifting 1.1 Experiment Objective Practice to use Quartus II to create new projects and use system resources IP Core; Proficiency in the writing of Verilog HDL programs to develop a good code writing style; Master the design of the frequency divider to implement the shifting LED; Combine hardware resources to perform FPGA pin assignment and implement actual program downloading; Observe the experiment result and summarize it. 1.2 Experiment Implement Use all LEDS, all light up during reset; End reset, LED lights from low to high (from right…

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Experimental Manuals FPGA for Beginners Pocket Boards PRA006/PRA010

Understand What Ethernet is and How it Works, the Relationship Between Different Interface Types (MII, GMII, RGMII) , Ethernet Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 14

Experiment 14 Ethernet Experiment 14.1 Experiment Objective Understand what Ethernet is and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (the development board uses RGMII) Combine the development board to complete the transmission and reception of data and verify it 14.2 Experiment Implement Perform a loopback test to check if the hardware is working properly. Performing data verification Perform data transmission verification 14.3 Experiment 14.3.1 Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method…

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Experimental Manuals FPGA for Beginners FPGA Tutor PRA006/PRA010

Design a simple customized VGA image display, Master the principle of VGA implementation, VGA Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 13

Experiment 13 VGA Experiment 13.1 Experiment Objective Master the principle of VGA implementation Design a simple customized VGA image display 13.2 Experiment Implement A color bar graphic is implemented on the screen. 13.2 Experiment 13.2.1 VGA Principle VGA (Video Graphics Array) is a computer display standard that IBM introduced in 1987 using analog signals. VGA is a low standard that is supported by most manufacturers. PCs must support the VGA standard before loading their own unique drivers. The VGA scanning mode on the display is divided into progressive scanning and…

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Experimental Manuals FPGA for Beginners FPGA Tutor PRA006/PRA010

The knowledge of the IIC protocol, the Theory of AD Conversion, AD, DA Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 12

Experiment 12 AD, DA Experiment 12.1 Experiment Objective Since in the real world, all naturally occurring signals are analog signals, and all that are read and processed in actual engineering are digital signals. There is a process of mutual conversion between natural and industrial signals (digital-to-analog conversion: DAC, analog-to-digital conversion: ADC). The purpose of this experiment is as follows: Learn about the theory of AD conversion Review the knowledge of the IIC protocol learned in the previous experiment and write the data into PCF8591 on the development board. Read the…

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FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Reading and Writing EEPROM, the Basic Principles of Asynchronous IIC Bus, the IIC Communication Protocol, IIC transmitting Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 11

Experiment 11 IIC transmitting Experiment 11.1 Experiment Objective Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 11.2 Experiment Implement Correctly write a number to any address in the EEPROM (this experiment writes to the register of 8’h03 address) through the FPGA (here changes the written 8-bit data value by (SW7~SW0)). After writing in successfully, read the data as well. The read data is displayed directly on the segment display. Program the FPGA…

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