- Review IIC protocol
- Review EEPROM read and write
- Learn HDMI principle
Display different image content on the screen through the HDMI.
Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. HDMI (High Definition Multimedia Interface) is a digital video/audio interface technology. It is a dedicated digital interface for image transmission. It can transmit audio and video signals at the same time.
The ADV7511 is a chip that converts FPGA digital signal to HDMI signal following VESA standard. For more details, see the related chip manual. Among them, “ADV7511 Programming Guide” and “ADV7511 Hardware Users Guide” are the most important. The registers of the ADV7511 can be configured by referring those documents.
ADV7511 Register Configuration Description: The bus inputs D0-D3, D12-D15, and D24-D27 of the ADV7511 have no input, and each bit of data is in 8-bit mode. Directly set 0x15 [3:0]) 0x0 data, 0x16 [3:2] data does not need to be set for its mode. Set [5:4] of 0X16 to 11for 8-bit data and keep the default values for the other digits. 0x17 refers to the ratio of the length to the width of the image. It can be set to 0 or 1. The actual LCD screen will not change according to the data but will automatically stretch the full screen mode according to the LCD’s own settings. 0x18 is the way to start the color range stretching. The design is that RGB maps directly to RGB, so it can be disabled directly. 0X18[6:5] is also invalid currently. 0XAF  is to set HDMI or DVI mode, the most direct point of HDMI than DVI is that HDMI can send digital audio data and encrypted data content. This experiment only needs to Display the picture, and it can be set directly to DVI mode. Set 0XAF  to 0 to turn off HDMI encryption. Due to GCCD, deep color encryption data is not applicable, so the GC option is turned off. 0x4c register does not need to be set as well. Other sound data setting can be ignored here for DVI output mode. After writing these registers, the image can be displayed successfully.
The onboard HDMI module consists of an HDMI interface and an ADV7511 chip. The physical photo is shown in Figure 13.1. The schematics is shown in Figure 13.2.
Figure 13.1 HDMI interface and ADV7511 chip physical photo
Figure 13.2 Schematics of HDMI
ADV7511 chip is set through the IIC bus and send the picture information to be displayed to the chip through HDMI_D0 to HDMI_D23, and control signals HDMI_HSYNC and HDMI_VSYNC and the clock signal HDMI_CLK, which are transmitted to the PC through the HDMI interface after being processed internally by the chip.
The configuration part of the ADV7511 chip is carried out using the IIC protocol, with reference to Experiment 11 and Experiment 12. A brief introduction to the data processing section is now available.
The FPGA configures the ADV7511 chip through the IIC bus (clock line scl, data line sda). After the configuration is completed, the output image information needs to be determined. Taking the 1080P (1920*1080) image format as an example, it outputs data signal rgb_r (red component), rgb_g (green component), rgb_b (blue component), a line sync signal rgb_hs, a field sync signal rgb_vs, and a clock rgb_clk signal. Each pixel is formed by a combination of three color components. Each row of 1920 pixels is filled with color information in a certain order (from left to right) and begin to fill the next line after completing one line, in a certain order (from top to bottom) to finish 1080 lines, so that one frame of image information is completed. The image information of each frame is determined by this horizontal and vertical scanning, and then transmitted to the ADV7511 for processing. The timing diagram of the horizontal and vertical scan is shown in Figure 13.3, Figure 13.4.
Figure 13.3 Horizontal synchronization
Figure 13.4 Vertical synchronization
The second step: data definition of 1080p image timing generation
The third step: Generate display content
When the button is pressed, a key1 signal will be input, and the content displayed on the screen will change according to the change of vga_dis_mode, and the corresponding picture content will be displayed.
The first step: pin assignment
Table 13.1 HDMI Experiment Pin Mapping
|Signal Name||Network Label||FPGA Pin||Port Description|
|clk||CLK_50M||G21||System clock 50 MHz|
|scl||I2C_SCL||D13||IIC clock line|
|sda||I2C_SDA||C13||IIC data line|
|key1||PB2||V5||Switch display content|
|vga_hs||HDMI_R_HS||B9||Horizontal sync signal|
|vg_vs||HDMI_R_VS||A9||Vertical sync signal|
The second step: board verification
After the pin assignment is completed, the compilation is performed, and the development board is programmed.
Press the push button and the display content changes accordingly. The experimental phenomenon is shown in the figure below (only a few are listed).
Figure 13.5 HDMI display (all white)
Figure 13.6 HDMI display (square)
Figure 13.7 HDMI display (color strip)