FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

How does SRAM read and write work ? Review frequency division, button debounce, and hex conversion experiment – FII-PRA040 Altera Risc-V Tutorial Experiment 15

Experiment 15 SRAM Read and Write

15.1 Experiment Objective

  1. Learn the read and write of SRAM
  2. Review frequency division, button debounce, and hex conversion experiment content

15.2 Experiment Implement

  1. Control the read and write function of SRAM by controlling the button
  2. The data written to the SRAM is read out again and displayed on the segment display
  3. In the process of reading data, it is required to have a certain time interval for each read operation.

15.3 Experiment

15.3.1 Introduction to SRAM

SRAM (Static Random-Access Memory) is a type of random access memory. The “static” means that as long as the power is on, the data in the SRAM will remain unchanged. However, the data will still be lost after power turned off, which is the characteristics of the RAM.

Two SRAMs (IS61WV25616BLL) are on the development board, each SRAM has 256 * 16 words of storage space. Each word is 16-bit. The maximum read and write speed can reach 100 MHz. The physical picture is shown in Figure 15.1.

Figure 15.1 SRAM physical picture

15.3.2 Hardware Design

As shown in Figure 15.2, a set of control signals (low signal is valid): chip selection signal CE, read control signal OE, write enable control number WE, and two byte control signals UB and LB, through CE_N_SRAM, OE_N_SRAM, WE_N_SRAM, UB_N_SRAM, LB_N_SRAM, connect to the FPGA, and the read and write status is controlled by the FPGA. The address is sent to the SRAM through the address line A[17:0]. In the write state, the data to be written is sent to the SRAM through the data line D[15:0], and can be written into the register of the corresponding address; In the read state, the data in the corresponding address register can be directly read into the FPGA by the data line.

Figure 15.2 Schematics of SRAM

15.3.3 Introduction to the Program

This experiment will use the frequency division, button debounce, hex conversion and segment display module. (Refer to the previous experiment for more information) Here SRAM read and write module is mainly introduced.

The first step: the establishment of the main program framework

module sram (

input IN_CLK_50M, //System clock on board

input [7:1] PB, //Push buttons

output sram0_cs_n, //First SRAM control signal group

output sram0_we_n,

output sram0_oe_n,

output sram0_ub_n,

output sram0_lb_n,

output sram1_cs_n, //Second SRAM control signal group

output sram1_we_n,

output sram1_oe_n,

output sram1_ub_n,

output sram1_lb_n,

output [17:0] sram_addr, //sram adress signal

inout [31:0] sram_data, //sram data signal

output [5:0] tube_sel, // Segment display control signal

output [7:0] tube_seg

);

endmodule

The inputs are 50 MHz system clock IN_CLK_50M, button module PB[7:1], PB[3] (RETURN) as external hardware reset, PB[2] (UP) as write control, PB[7] (DOWN) as read control. The output has two sets of control signals to control two srams respectively, specifically chip selection signal sram_cs_n, write control signal sram_we_n, read control signal sram_oe_n, and byte control signals sram_ub_n and sram_lb_n, address bus sram_daddr[17:0], data bus Sram_data[31:0], and the segment display bit selection signal tube_sel[5:0] and the segment selection signal tube_seg[7:0].

The second step: SRAM read and write module

In this experiment, two SRAMs are used simultaneously and are expanded into a 32-bit wide data memory.

reg [31:0] wr_data;

reg wr_en;

reg [3:0] state;

reg [7:1] PB_flag;

reg wr_done;

reg rd_done;

reg s_flag;

assign sram_data = wr_en ? wr_data : 32’hz;

always @ (posedge clk)

begin

if (!rst_n)

begin

wr_done <= 1’b0;

rd_done <= 1’b0;

rd_data <= 32’d0;

wr_data <= 32’d0;

sram0_cs_n <= 1’b1;

sram0_we_n <= 1’b1;

sram0_oe_n <= 1’b1;

sram0_ub_n <= 1’b1;

sram0_lb_n <= 1’b1;

sram1_cs_n <= 1’b1;

sram1_we_n <= 1’b1;

sram1_oe_n <= 1’b1;

sram1_ub_n <= 1’b1;

sram1_lb_n <= 1’b1;

sram_addr <= 18’d0;

wr_en <= 1’b0;

state <= 4’d0;

end

else

case(state)

0 :

begin

wr_done <= 1’b0;

rd_done <= 1’b0;

sram_addr <= 18’d511;

wr_data <= 32’d123456;

if (PB_flag[2])

begin

wr_en <= 1’b1;

state <= 4’d1;

sram0_cs_n <= 1’b0;

sram0_we_n <= 1’b0;

sram0_oe_n <= 1’b1;

sram0_ub_n <= 1’b0;

sram0_lb_n <= 1’b0;

sram1_cs_n <= 1’b0;

sram1_we_n <= 1’b0;

sram1_oe_n <= 1’b1;

sram1_ub_n <= 1’b0;

sram1_lb_n <= 1’b0;

end

else if (PB_flag[7])

begin

wr_en <= 1’b0;

state <= 4’d2;

sram0_cs_n <= 1’b0;

sram0_we_n <= 1’b1;

sram0_oe_n <= 1’b0;

sram0_ub_n <= 1’b0;

sram0_lb_n <= 1’b0;

sram1_cs_n <= 1’b0;

sram1_we_n <= 1’b1;

sram1_oe_n <= 1’b0;

sram1_ub_n <= 1’b0;

sram1_lb_n <= 1’b0;

end

else

state <= 4’d0;

end

1 :

begin

if (sram_addr == 18’d0)

begin

state <= 4’d4;

wr_done <= 1’b1;

wr_en <= 1’b0;

end

else

begin

state <= 4’d1;

sram_addr <= sram_addr – 1’b1;

wr_data <= wr_data – 1’b1;

end

end

2 :

begin

if (sram_addr == 18’d0)

state <= 4’d4;

else

state <= 4’d2;

if (s_flag)

begin

sram_addr <= sram_addr – 1’b1;

rd_data <= sram_data;

rd_done <= 1’b1;

end

else

rd_done <= 1’b0;

end

4 :

begin

sram0_cs_n <= 1’b1;

sram0_we_n <= 1’b1;

sram0_oe_n <= 1’b1;

sram0_ub_n <= 1’b1;

sram0_lb_n <= 1’b1;

sram1_cs_n <= 1’b1;

sram1_we_n <= 1’b1;

sram1_oe_n <= 1’b1;

sram1_ub_n <= 1’b1;

sram1_lb_n <= 1’b1;

wr_done <= 1’b0;

rd_done <= 1’b0;

state <= 0;

end

default : state <= 0;

endcase

end

In the write state, the write enable wr_en is pulled high. At this time, sram_data is the data wr_data to be written. In other cases, the write enable is pulled low. In the read state, the data is directly read into the FPGA by sram_data.

At reset, the SRAM control signals are all pulled high, then jumps to the 0 state, and the data is read and written by the state machine.

0 state: an initial address “511” is given, and an initial data “123456”, when the write enable signal PB_flag[2] is valid, the chip selection signal pulls down the selected SRAM. The write control signal is pulled low to prepare for write operation, and the read control signal remains pulled up. Meanwhile, the byte control signal is pulled low, indicating that the high and low two bytes of data are simultaneously written and then jump to the 1 state. When the read enable signal PB_flag[7] is active, in contrast to the write enable, the write control signal is held high, the read control signal is pulled low to prepare for the read operation, and jumps to the 2 state.

1 state: starting from the initial address “511”, writing initial data “123456”, each clock cycle address and data are simultaneously decremented by one, performing 512 data continuous write operations. When the register address bit is ‘0’, end the write operation and jum to the 4 state.

2 state: Starting from the initial address “511”, the address is decremented by 1 every 1 second under the control of the second pulse s_flag, and a continuous read operation of 512 data is performed. When the data is completely read, the address jumps to the 4 state when the address is ‘0’.

4 state: The control signals are all pulled high, deactivate the control of the SRAM, jumping to the ‘0’ state, an waiting for the next operation.

15.4 Experiment Verification

The first step: pin assignment

Table 15.1 SRAM read and write experiment pin mapping

Signal Name Network Label FPGA Pin Port Description
IN_CLK_50M CLK_50M G21 System clock 50 MHz
PB[1] PB[1] Y4 7 push buttons on board
PB[2] PB[2] V5
PB[3] PB[3] Y6
PB[4] PB[4] AB4
PB[5] PB[5] Y3
PB[6] PB[6] AA4
PB[7] PB[7] AB3
sram0_cs_n CE_N_SRAM0 F21 First SRAM control signal
sram0_we_n WE_N_SRAM0 B22
sram0_oe_n OE_N_SRAM0 F17
sram0_ub_n UB_N_SRAM0 K22
sram0_lb_n LB_N_SRAM0 K21
sram1_cs_n CE_N_SRAM1 N22 Second SRAM control signal
sram1_we_n WE_N_SRAM1 R19
sram1_oe_n OE_N_SRAM1 Y21
sram1_ub_n UB_N_SRAM1 Y22
sram1_lb_n LB_N_SRAM1 T18
sram_addr[0] A_R_0 J21 SRAM address line
sram_addr[1] A_R_1 H22
sram_addr[2] A_R_2 H19
sram_addr[3] A_R_3 G18
sram_addr[4] A_R_4 H17
sram_addr[5] A_R_5 H21
sram_addr[6] A_R_6 H20
sram_addr[7] A_R_7 F19
sram_addr[8] A_R_8 H18
sram_addr[9] A_R_9 F20
sram_addr[10] A_R_10 W21
sram_addr[11] A_R_11 W22
sram_addr[12] A_R_12 V21
sram_addr[13] A_R_13 U20
sram_addr[14] A_R_14 V22
sram_addr[15] A_R_15 R21
sram_addr[16] A_R_16 U21
sram_addr[17] A_R_17 R22
sram_addr[18] A_R_18 U22
sram_data[0] D_R_0 F22 SRAM data line
sram_data[1] D_R_1 E21
sram_data[2] D_R_2 D21
sram_data[3] D_R_3 E22
sram_data[4] D_R_4 D22
sram_data[5] D_R_5 C21
sram_data[6] D_R_6 B21
sram_data[7] D_R_7 C22
sram_data[8] D_R_8 M16
sram_data[9] D_R_9 K19
sram_data[10] D_R_10 M20
sram_data[11] D_R_11 M19
sram_data[12] D_R_12 L22
sram_data[13] D_R_13 L21
sram_data[14] D_R_14 J22
sram_data[15] D_R_15 J18
sram_data[16] D_R_16 M21
sram_data[17] D_R_17 K18
sram_data[18] D_R_18 N21
sram_data[19] D_R_19 M22
sram_data[20] D_R_20 P22
sram_data[21] D_R_21 P20
sram_data[22] D_R_22 R20
sram_data[23] D_R_23 P21
sram_data[24] D_R_24 W19
sram_data[25] D_R_25 W20
sram_data[26] D_R_26 R17
sram_data[27] D_R_27 T17
sram_data[28] D_R_28 U19
sram_data[29] D_R_29 AA21
sram_data[30] D_R_30 AA22
sram_data[31] D_R_31 R18
tube_sel[0] SEG_3V3_D0 F14
Segment display bit selection signal
tube_sel[1] SEG_3V3_D1 D19
tube_sel[2] SEG_3V3_D2 E15
tube_sel[3] SEG_3V3_D3 E13
tube_sel[4] SEG_3V3_D4 F11
tube_sel[5] SEG_3V3_D5 E12
tube_seg[0] SEG_PA B15 Segment display segment selection signal
tube_seg[1] SEG_PB E14
tube_seg[2] SEG_PC D15
tube_seg[3] SEG_PD C15
tube_seg[4] SEG_PE F13
tube_seg[5] SEG_PF E11
tube_seg[6] SEG_PG B16
tube_seg[7] SEG_DP A16

The second step: board verification

After the pin assignment is completed, the compilation is performed, and the board is verified after passing.

After the development board is programmed, the segment display will all light up, but because no data is read, the segment display will display all ‘0’s, as shown in Figure 15.3. Press the PB[2] (UP) button to write the data to the SRAM, and then press the PB[7] (DOWN) button to read the written data.

At this time, it displays “123456” and decrement by one every second.

See Figure 15.4. From this it is verified that the specified data is written into the SRAM and is read correctly.

Figure 15.3 SRAM write and read 1

Figure 15.4 SRAM write and read 2

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