FPGA Products - Part 4

C Programming (1) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)

November 9, 2020November 9, 2020 beginner FPGA32 registers, ARTIX-7, C Project Compilation Process, CPU, FII-PRX100, FII-RISCV CPU, Freedom Studio, Linker functionality, XC7A100T, XILINX FPGA Board

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board C Programming 1 Version Control Version Date Description 1.0 10/24/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

Risc-V Bus and PipeLine – FII Risc-V Bus and Pipeline Design – Risc-V Tutorial and Exercise

November 9, 2020November 9, 2020 beginner FPGABus, FII Risc-V Bus and Pipeline Design, PipeLine, Risc-V, Risc-V Exercise, Risc-V Tutorial

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board Bus and Pipeline Version Control Version Date Description 1.0 10/28/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…

Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Evaluation by Coremark and Dhrystone Benchmarks

October 8, 2020November 9, 2020 SteveGuysARTIX-7, CPU Processor, FII RISC-V3.01, FII RISC-V3.01 CPU Processor, FII-PRX100-S, XC7A100T, XILINX FPGA Board Evaluation

V1.1 Fraser Innovation inc FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Evaluation Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/07/2020 Add Description of PRX100 and Comparison Plots Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using…

Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

Dhrystone Porting Guide For FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board

October 8, 2020January 19, 2021 SteveGuysARTIX-7, CPU Processor, Dhrystone Porting Guide, FII-PRX100-S, Risc-V Processor, RISC-V3.01 CPU Processor, XC7A100T, XILINX FPGA Board

V1.1 Fraser Innovation inc Dhrystone Porting Guide For FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/07/2020 Add Description of PRX100 and Comparison Plot Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual…

Experimental Manuals FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D FPGA Board Based PRX100 Risc-V Core Risc-V Tutorial

FII RISC-V3.01 CPU Processor on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Porting Guide

October 8, 2020February 1, 2021 SteveGuysCoremark Porting, CPU Processor, FII-PRX100-S, Risc-V, RISC-V3.01, XILINX FPGA Board

V1.1 Fraser Innovation inc FII RISC-V3.01 on FII-PRX100-S (ARTIX-7, XC7A100T) XILINX FPGA Board Coremark Porting Guide Version Control Version Date Description 1.0 09/29/2020 Initial Release 1.1 10/06/2020 Add Comparison Figure and Full Description of PRX100 Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual…

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Board Based PRX100 Risc-V

Xinlix Risc-V Board PRX100-S, PRX100-D Experimental Manuals (2019-12-19 Version ) with twenty experiments

October 3, 2020November 9, 2020 SteveGuysExperimental Manuals, PRX100-D, PRX100-S, Risc-V Board, Xinlix

Xinlix Risc-V Board PRX100-S, PRX100-D Experimental Manuals (2019-12-19 Version ) with twenty experiments

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Board Based FPGA Tutor PRX100 Risc-V

DAC9767 DDS Signal Source Experiment – Xilinx Risc-V Board FII-PRX100 Experiment 20

October 3, 2020 SteveGuysAD9767 datasheet, DDS Introduction, DDS Signal Source Experiment, Direct Digital Synthesizer)

Experiment 20 DAC9767 DDS Signal Source Experiment 20.1 Experiment Objective Learn about DDS (Direct Digital Synthesizer) related theoretical knowledge. Read the AD9767 datasheet and use the AD9767 to design a signal source that can generate sine, square, triangle, and sawtooth waves. 20.2 Experiment Implement Learn about DDS theoretical knowledge. On the basis of understanding the principle of DDS, combined with the theoretical knowledge, use AD9767 module and development board to build a signal source whose waveform, amplitude and frequency can be adjusted. (There are no specific requirements for the adjustment…

Signal waveform of AD9226 captured by logic analyzer

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Board Based FPGA Tutor PRX100 Risc-V

High-speed ADC9226 Acquisition Experiment – Xilinx Risc-V Board FII-PRX100 Experiment 19

October 3, 2020 SteveGuysAD acquisition sub-module, ADC9226 Acquisition Experiment

Experiment 19 High-speed ADC9226 Acquisition Experiment 19.1 Experiment Objective Learn about parallel ADC collectors and master the use of ADC9226. 19.2 Experiment Implement 1. Insert the ADC9226 module face up into the FPGA development board to the GPIO2 and GPIO1 ports which are next to the red-green audio module. Write programs to use this module to test 19.3 Experiment 19.3.1 ADC9226 Module Introduction ADC9226 module adopts AD9226 chip design of ADI Company. This chip is a monolithic, 12-bit, 65 MSPS analog-to-digital converter (ADC). It uses a single power supply and…

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Board Based PRX100 Risc-V

Photo Display Experiment of OV5640 Camera , Understand the power-on sequence of the OV5640 camera and the corresponding register configuration process – Xilinx Risc-V Board FII-PRX100 Experiment 18

October 3, 2020 SteveGuysHDMI, IIC bus, OV5640 Camera, OV5640 datasheet, OV5640 related registers, power-on timing diagram

Experiment 18 Photo Display Experiment of OV5640 Camera 18.1 Experiment Objective Understand the power-on sequence of the OV5640 camera and the corresponding register configuration process when outputting images of different resolutions Review previous knowledge of IIC bus Review previous knowledge of HDMI 18.2 Experiment Implement Read the power-on sequence of the OV5640 datasheet, and correctly write the power-on control program according to the peripheral module schematics. Correctly write the configuration program of the OV5640 camera with a resolution of 640X480 according to the timing requirements of the SCCB interface Based…

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Board Based PRX100 Risc-V

Reading Experiment of Serial Port Partition of Static Memory SRAM, Read and write timing of IS61WV25616BLL SRAM, and prepare for the next experimental experiment of OV5640 camera experiment – – Xilinx Risc-V FII-PRX100 Board Experiment 17

October 3, 2020 SteveGuys18-bit address, 32-bit data space, IS61WV25616BLL SRAM, Serial Port Partition, SRAM, Static Memory SRAM

Experiment 17 Reading Experiment of Serial Port Partition of Static Memory SRAM 17.1 Experiment Objective Learn about static memory SRAM read and write operations and how it works Familiar with the read and write timing of IS61WV25616BLL SRAM, and prepare for the next experimental experiment of OV5640 camera experiment. 17.2 Experiment Implement The experimental board is equipped with two pieces of SRAM, which are combined to form 18-bit address lines and 32-bit data spaces. After power-on, the FPGA will write the same value in the corresponding address in the entire…