FPGA Products - Part 3

Study the Format of .mif File and How to Edit .mif File ，Study the Internal Memory Block of FPGA，Use of ROM – FPGA Beginner Study Board PRA006, PRA010 Experiment 8

FPGA Beginner Study Board, How to Edit *.mif File, PRA006, PRA010, the Format of *.mif File, the Internal Memory Block of FPGA, Use of ROM

Experiment 8 Use of ROM 8.1 Experiment Objective Study the internal memory block of FPGA Study the format of *.mif and how to edit *.mif file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Implement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment display illustrates the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Introduction to Program This experiment was carried out on the basis of Experiment 7, and…

Experimental Manuals FPGA Board Based FPGA for Beginners PRA006/PRA010

Binary Numbers or Hexadecimal Number to BCD Code Conversion and Application – FPGA Beginner Study Board PRA006, PRA010 Experiment 7

BCD Code, Binary Numbers, FPGA Beginner Study Board, Hexadecimal Number, PRA006, PRA010

Experiment 7 Hexadecimal Number to BCD Code Conversion and Application Experiment Objective Learn to convert binary numbers to BCD code (bin_to_bcd) Learn to convert hexadecimal numbers to BCD code (hex_to_bcd) 7.2 Experiment Implement Combined with experiment 6, display the results of the operation to the segment display. 7.3 Experiment 7.2.1 Introduction to the Principle of Converting Hexadecimal Number to BCD Code Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eyes recognition is relatively slow, so the display from hexadecimal to decimal…

Experimental Manuals FPGA for Beginners FPGA Tutor PRA006/PRA010

Use ModelSim Simulation to Design Output, Use of Multipliers and ModelSim Simulation – FPGA Beginner Study Board PRA006, PRA010 Experiment 6

FPGA Beginner Study Board, PRA006, PRA010, Use ModelSim Simulation to Design Output, Use of Multipliers and ModelSim Simulation

Experiment 6 Use of Multipliers and ModelSim Simulation 6.1 Experiment Objective Learn to use multiplier Use ModelSim simulation to design output 6.2 Experiment Implement 8×8 multiplier, the first input value is an 8-bit switch, and the second input value is the output of an 8-bit counter. Observe the output in ModelSim Oberseve the calculation results with a four-digit segment display 6.3 Experiment Since the simulation tools and the new IP core are used here, there is no introduction or design part of hardware. 6.3.1 Introduction of Program ModelSim is an…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

Button Debounce Principle and Adaptive Programming – Button Debounce Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 5

Adaptive Programming, Button Debounce, Button Debounce Experiment, Button debounce experiment phenomenon, button debounce principle, FPGA Beginner Study Board, PRA006, PRA010

Experiment 5 Button Debounce Experiment 5.1 Experiment Objective Review the design process of the shifting LED Learn button debounce principle and adaptive programming Study the connection and use of the FII-PRA006/010 button hardware circuit Comprehensive application button debounce and other conforming programming 5.2 Experiment Implement Control the movement of the lit LED by pressing the button Each time the button is pressed, the lit LED moves one bit. When the left shift button is pressed, the lit LED moves to the left, presses the right button, and the lit LED…

Experimental Manuals FPGA Board Based FPGA for Beginners PRA006/PRA010

Building new FPGA Projects in Quartus, Device Selection, PLL setup, PLL Frequency Setting, Verilog’s Tree Hierarchy Design, and the Use of SignalTap II – Block/SCH Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 4

Block/SCH Experiment, device selection, FPGA Beginner Study Board, PLL frequency setting, PLL setup, PRA010, Quartus, SignalTap II, Verilog's Tree Hierarchy Design

Experiment 4 Block/SCH Experiment 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL setup, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

Use the BCD Code Counter, Digital Display Decoding Design, the Serial Flash, – Segment Display – FPGA Beginner Study Board PRA006, PRA010 Experiment 3

BCD Code Counter, Digital Display Decoding Design, FPGA Beginner Study Board, PRA006, PRA010 Experiment 3, segment display, the Serial Flash

Experiment 3 Segment Display 3.1 Experiment Objective Review previous experiments, proficient practice in PLL configuration, frequency division design, and project verification; Learn to use the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower (right most) digits to display seconds, the middle two digits to display minutes, and the highest (left most) two digits to display hours. The decimal point remains off and will not be considered for the time…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

The Use of SignalTap Logic Analyzer, Analyze the Captured Signals – FPGA Beginner Study Board PRA006, PRA010 Experiment 2

Analyze the Captured Signals, FPGA Beginner, Logic Analyzer, PRA006, PRA010, SignalTap, Study Board

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice using of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Capture and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction to the Switches and SignalTap Introduction to the switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the circuit by turning the switch handle using the binary coding…

FPGA for Beginners PRA006/PRA010

LED shifting, Using Quartus, the Writing of Verilog HDL programs, Mange FPGA Pin Assignment – FPGA Beginner Study Board PRA006, PRA010 Experiment 1

FPGA, FPGA Begiiner Board, FPGA Study Board, HDL programs, LED shifting, Mange FPGA Pin Assignment, PRA006, PRA010, Schematics of LED, Using Quartus, verilog

Experiment 1 LED shifting 1.1 Experiment Objective Practice using the development software Quartus, the building of new projects, and the use of system resources IP Core; Proficiency practice in the writing of Verilog HDL programs to develop a fine code writing style; Master the design of the frequency divider to realize the design of LED shifting; Mange FPGA pin assignment according to the schematics, and verify it though programming the development board; Observe and summarize the experiment result 1.2 Experiment Implement All LEDs are lit up when pressing self-defined reset…

Experimental Manuals FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

FPGA for Beginner Board Experimental Manuals and Study Guide – PRA006, PRA010 FPGA Beginner Study Board

Fraser Innovation Inc FII-PRA006/010 User Experimental Manual Version Control Version Date Descrption V1.0 10/07/2019 Initial Release V1.1 12/07/2019 Add figures for corresponding experimental phonomena of experiment board V1.2 30/08/2019 Modify part of pin assignments and Ethernet description Project Files Content Experiment 1: LED_shifting Experiment 2: SW_LED Experiment 3: BCD_counter Experiment 4: block_counter Experiment 5: block_debouncing Experiment 6: mult_sim Experiment 7: HEX_BCD, HEX_BCD_mult Experiment 8: memory_rom Experiment 9: dual_port_ram Experiment 10: UART_FRAME Experiment 11: eeprom_test Experiment 12: adda_test Experiment 13: vga Experiment 14: Ethernet Part One: Introduction to FII-PRA006/010…

FII RISC-V3.01 CPU FII-PRA040 FII-PRX100-S FII-PRX100D PRX100 Risc-V Risc-V Core Risc-V Tutorial

C Programming (2) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)

Create a new C project, FII-Risc-V CPU, FPGA Board, RISCV_seg_irq Project

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board C Programming 2 Version Control Version Date Description 1.0 10/17/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…