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High-speed ADC9226 Acquisition Experiment (FII-BD9226) – parallel ADC collectors and master the use of ADC9226 – FII-PRA040 Altera Risc-V Experiment 18


Experiment 18 High-speed ADC9226 Acquisition Experiment

18.1 Experiment Objective

Learn about parallel ADC collectors and master the use of ADC9226.

18.2 Experiment Implement

Insert the ADC9226 module face up into the FPGA development board to the GPIO2 and GPIO1 ports which are next to the red-green audio module. Write programs to use this module to test

18.3 Experiment

18.3.1 ADC9226 Module Introduction

ADC9226 module adopts AD9226 chip design of ADI Company. This chip is a monolithic, 12-bit, 65 MSPS analog-to-digital converter (ADC). It uses a single power supply and has an on-chip high-performance sample-and-hold amplifier and voltage reference. It uses a multistage differential pipelined architecture with a data rate of 65 MSPS and guarantees no missing codes over the full operating temperature range.

See Figure 18.1 for ADC9226 timing diagram.

FPGA development board
Figure18.1 ADC9226 timing diagram

From this timing diagram, we know that there is no need to configure the AD9226 chip, as long as the appropriate CLOCK is provided, the chip can perform data acquisition.

18.3.2 Program Design

        1. AD acquisition sub-module

As can be seen from Figure 18.1, the high bit of AD9226 is bit[0] and the low bit is bit [11], so the data bit order needs to be reversed in the program.

module ad_9226(

input ad_clk,

input [11:0] ad1_in,

output reg [11:0] ad_ch


always @(posedge ad_clk)


ad_ch[11] <= ad1_in[0] ;

ad_ch[10] <= ad1_in[1] ;

ad_ch[9 ] <= ad1_in[2] ;

ad_ch[8 ] <= ad1_in[3] ;

ad_ch[7 ] <= ad1_in[4] ;

ad_ch[6 ] <= ad1_in[5] ;

ad_ch[5 ] <= ad1_in[6] ;

ad_ch[4 ] <= ad1_in[7] ;

ad_ch[3 ] <= ad1_in[8] ;

ad_ch[2 ] <= ad1_in[9] ;

ad_ch[1 ] <= ad1_in[10] ;

ad_ch[0 ] <= ad1_in[11] ;



        1. Data conversion program

The AD9226 module design uses an internal reference source. VREF is the output port of the reference source, which can be used for 1V and 2V reference voltages. It can be selected through SENCE. When SENCE is grounded, a 2V reference is provided, and when SENCE is connected to VREF, a 1V reference is provided. The module uses a 2V reference power supply. VINA input range is 1.0 ~ 3.0V.

The 22 (12) pin of AD9226 has the function of collecting data selection. There are two input and output data formats of AD9226. For the specific format, refer to the 9226 datasheet. The 22 (12) pin of the AD9226 module in this experiment is connected to high level, so it uses Binary Output Mode. The BCD conversion submodule has been introduced in Experiment 8 and is not repeated here.

module volt_cal(input wire ad_clk,input wire [11:0] ad_ch1,output [19:0] ch1_dec,output reg ch1_sig);

reg [31:0] ch1_data_reg;

reg [11:0] ch1_reg;

reg [31:0] ch1_vol;

always @(posedge ad_clk)


if(ad_ch1[11]==1’b1) begin


ch1_sig <= 0;


else begin





always @(posedge ad_clk)


ch1_data_reg<=ch1_reg * 2000;

ch1_vol<=ch1_data_reg >>11;


bcd bcd1_ist(

.hex (ch1_vol[15:0]),

.dec (ch1_dec),

.clk (ad_clk)



        1. 9226 module AD acquisition range selection

The attenuation range of the AD acquisition module is divided into gears. Press the UP key on the development board to switch the range.

Table 18.1 Gear shift indication table

Gear comparison table (input voltage percentage)
Corresponding indicator
4% led0 lit
8% led0, led1 lit
20% led0, led1, led2 lit
40% led0, led1, led2, led2 lit
module range (

input wire clk ,

input wire rst_n ,

input wire key ,

output wire [3:0] led ,

output wire [1:0] scope


wire flag_switch ;

key_process key_process_inst(

.clk (clk) ,

.rst_n (rst_n) ,

.key_switch (key) ,

.flag_switch (flag_switch)


reg [1:0] scope_st =00 ;

reg [3:0] led_temp =4’he ;

always @ (posedge clk ,negedge rst_n)


if (~rst_n)


scope_st <= 0 ;

led_temp <= 4’he ;


else begin

case (scope_st)

0: begin

led_temp <= 4’he ;

if (flag_switch )

scope_st <= 1 ;


1: begin

led_temp <= 4’hc ;

if (flag_switch )

scope_st <= 2 ;


2: begin

led_temp <= 4’h8 ;

if (flag_switch )

scope_st <= 3 ;


3: begin

led_temp <= 4’h0 ;

if (flag_switch )

scope_st <= 0 ;





assign led = led_temp ;

assign scope = scope_st ;


        1. Main program design

The main program is divided into three sub-programs, which are AD_9226 acquisition module, data conversion calculation module volt_cal, and voltage value segment display module. The segment display part has been introduced in the previous experiment and will not be introduced here.

module high_speed_ad_test(

input wire sys_clk,

input wire otr ,

input wire key_switch ,

input wire sys_rst_n ,

input wire [11:0] ad1_in,

output wire ad1_clk,

output wire [5:0] sel,

output wire [3:0] led ,

output wire cain_a,

output wire cain_b,

output wire [7:0] sm_db


assign ad1_clk = sys_clk ;

assign sm_db={point1, ~sm_db_r };

wire [19:0] ch1_dec;

wire [11:0] ad_ch1 ;

wire ch1_sig ;

wire point1 ;

wire [6:0] sm_db_r ;

ad_9226 u1 (

.ad_clk (sys_clk),

.ad1_in (ad1_in ),

.ad_ch (ad_ch1 )


volt_cal u2(

.ad_clk (sys_clk),

.ad_ch1 (ad_ch1),

.ch1_dec (ch1_dec),

.ch1_sig (ch1_sig)


led_seg7 u3(

.clk (sys_clk),

.rst_n (sys_rst_n ),

.otr (otr) ,

.ch1_sig (ch1_sig ),

.ch1_dec (ch1_dec),

.sel (sel),

.point1 (point1),

.sm_db (sm_db_r)


range u4(

.clk (sys_clk),

.rst_n (sys_rst_n ),

.key (key_switch) ,

.led (led),

.scope ({cain_b,cain_a})



18.4 Experiment Verification

  1. Pin assignment
Signal Name Port Description Network Name FPGA Pin
sys_clk System clock C10_50MCLK G21
sys_rst_n System reset KEY1 Y4
lg_en ADG612 input IO25 AB20
hg_en ADG612 input IO24 AA20
ad1_clk Ad acquisition clock IO28 R16
otr Input voltage overrange flag IO1 AA13
sm_db[0] Segment selection SEG_PA B15
sm_db[1] Segment selection SEG_PB E14
sm_db[2] Segment selection SEG_PC D15
sm_db[3] Segment selection SEG_PD C15
sm_db[4] Segment selection SEG_PE F13
sm_db[5] Segment selection SEG_PF E11
sm_db[6] Segment selection SEG_PG B16
sm_db[7] Segment selection SEG_DP A16
sel[0] Bit selection SEG_3V3_D0 E12
sel[1] Bit selection SEG_3V3_D1 F11
sel[2] Bit selection SEG_3V3_D2 E13
sel[3] Bit selection SEG_3V3_D3 E15
sel[4] Bit selection SEG_3V3_D4 D19
sel[5] Bit selection SEG_3V3_D5 F14
ad1_in[0] AD9226 acquisition data bus IO0 V12
ad1_in[1] AD9226 acquisition data bus IO5 Y13
ad1_in[2] AD9226 acquisition data bus IO4 AB13
ad1_in[3] AD9226 acquisition data bus IO3 AB14
ad1_in[4] AD9226 acquisition data bus IO6 W13
ad1_in[5] AD9226 acquisition data bus IO2 R14
ad1_in[6] AD9226 acquisition data bus IO7 AA14
ad1_in[7] AD9226 acquisition data bus IO29 U16
ad1_in[8] AD9226 acquisition data bus IO30 AA15
ad1_in[9] AD9226 acquisition data bus IO31 T16
ad1_in[10] AD9226 acquisition data bus IO27 V16
ad1_in[11] AD9226 acquisition data bus IO26 U17
led0 Input signal attenuation indicator LED0 J5
led1 Input signal attenuation indicator LED1 J6
led2 Input signal attenuation indicator LED2 H5
led3 Input signal attenuation indicator LED3 H6
key_switch Attenuation switch PB2 V5
  1. Board verification

Use this experimental development board to connect the DA9667 module to generate a 1M sine wave as a signal source. Use the AD9226 module to connect to GPIO1 and GPIO2 of the PRA040 development board and apply a logic analyzer to capture the signal as shown in Figure 18.2. The following waveform can be observed. From the left to the right of the segment display, the first segment display is selected and lit to indicate that the input measurement voltage exceeds the AD9226 measurement range (the absolute value of VINA-VINB is less than or equal to the reference voltage, and the reference voltage of this module is 2V). The second segment display shows the sign of the input voltage (VINA-VINB). The last four digits are the input voltage value. When the input signal value is a slowly changing signal, the segment display can display the signal voltage amplitude.

Figure 18.2 Measured signal waveform of AD9226 captured by logic analyzer

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