SteveGuys | Fraser Innovation Inc

Altera RISC-V SoC AI FII-PRA040 FPGA development Board

Atera Risc-V FII-PRA040 Experimental Manuals ( 1- 20 ) PDF Version 2019-12-30

September 30, 2020 SteveGuysAtera, Experimental Manuals, FII-PRA040, Risc-V

Atera Risc-V FII-PRA040 Experimental Manuals ( 1- 20 ) PDF Version 2019-12-30 Version

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

High-speed ADC9226 Acquisition Experiment (FII-BD9226) – parallel ADC collectors and master the use of ADC9226 – FII-PRA040 Altera Risc-V Experiment 18

September 30, 2020February 1, 2021 SteveGuysAD9226 chip, ADC9226 Module, ADI Company, FII-BD9226, FPGA development board, High-speed ADC9226 Acquisition Experiment, parallel ADC collectors

Experiment 18 High-speed ADC9226 Acquisition Experiment 18.1 Experiment Objective Learn about parallel ADC collectors and master the use of ADC9226. 18.2 Experiment Implement Insert the ADC9226 module face up into the FPGA development board to the GPIO2 and GPIO1 ports which are next to the red-green audio module. Write programs to use this module to test 18.3 Experiment 18.3.1 ADC9226 Module Introduction ADC9226 module adopts AD9226 chip design of ADI Company. This chip is a monolithic, 12-bit, 65 MSPS analog-to-digital converter (ADC). It uses a single power supply and…

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

OV5640 Camera Photo Display Experiment, IIC bus, HDMI, Understand the power-on sequence of the OV5640 – FII-PRA040 Altera Risc-V Experiment 17

September 30, 2020February 1, 2021 SteveGuys5640 power-on sequence, HDMI, IIC bus, OV5640 Camera, OV5640 Camera Photo Display Experiment, OV5640 datasheet, register configuration process

Experiment 17 Photo Display Experiment of OV5640 Camera 17.1 Experiment Objective Understand the power-on sequence of the OV5640 camera and the corresponding register configuration process when outputting images of different resolutions Review previous knowledge of IIC bus Review previous knowledge of HDMI 17.2 Experiment Implement Read the power-on sequence of the OV5640 datasheet, and correctly write the power-on control program according to the peripheral module schematics. Correctly write the configuration program of the OV5640 camera with a resolution of 640X480 according to the timing requirements of the SCCB interface Based…

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Audio 8978 Loopback Experiment (WM8978 Audio Sub Development Board) , How I2S (Inter-IC Sound) bus work ? – – FII-PRA040 Altera Risc-V Tutorial Experiment 16

September 30, 2020September 30, 2020 SteveGuysAudio Bus Protocol, Audio Loopback Experiment, Control Interface Timing, I2S protocol, Inter-IC Sound Bus, MODE pin, WM8978, wm8978 board verification

Experiment 16 8978 Audio Loopback Experiment 16.1 Experiment Objective Learn about I2S (Inter-IC Sound) bus and how it works Familiar with the working mode of WM8978. And by configuring the interface mode and selecting the relevant registers in combination with the development board, complete the data transmission and reception, and verify it 16.2 Experiment Implement Perform audio loopback test by configuring the onboard audio chip WM8978 to check if the hardware is working properly Adjust the volume output level with the keys. 16.3 Experiment 16.3.1 WM8978 Introduction WM8978 is a…

FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

How does SRAM read and write work ? Review frequency division, button debounce, and hex conversion experiment – FII-PRA040 Altera Risc-V Tutorial Experiment 15

September 30, 2020September 30, 2020 SteveGuysButton Debounce, frequency division, hex conversion, How does SRAM read and write, pin assignment, Schematics of SRAM, SRAM read and write

Experiment 15 SRAM Read and Write 15.1 Experiment Objective Learn the read and write of SRAM Review frequency division, button debounce, and hex conversion experiment content 15.2 Experiment Implement Control the read and write function of SRAM by controlling the button The data written to the SRAM is read out again and displayed on the segment display In the process of reading data, it is required to have a certain time interval for each read operation. 15.3 Experiment 15.3.1 Introduction to SRAM SRAM (Static Random-Access Memory) is a type of…

FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

How does Ethernet work? MII, GMII, RGMII interface advantages and disadvantages, Perform a loopback test, FII-PRA040 Altera Risc-V Tutorial Experiment 14

September 30, 2020September 30, 2020 SteveGuysGMII interface, How does Ethernet work, Loopback test design, MII interface, RGMII interface, RGMIIRGMII, RTL8211E-VB

Experiment 14 Ethernet 14.1 Experiment Objective Understand what Ethernet is and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (FII-PRA040 uses RGMII) Combine the development board to complete the transmission and reception of data and verify it 14.2 Experiment Implement Perform a loopback test to check if the hardware is working properly. Perform data receiving verification Perform data transmission verification 14.3 Experiment 14.3.1 Introduction to Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method…

HDMI interface and ADV7511 chip physical photo

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Learn HDMI principle, Introduction to HDMI and ADV7511 Chip, HDMI Display, FII-PRA040 Altera Risc-V tutorial Experiment 13

September 30, 2020September 30, 2020 SteveGuysADV7511 Chip, ADV7511 Hardware Users Guide, ADV7511 Programming Guide, HDMI, IIC bus, IIC protocol, Schematics of HDMI, Vertical synchronization

Experiment 13 HDMI Display 13.1 Experiment Objective Review IIC protocol Review EEPROM read and write Learn HDMI principle 13.2 Experiment Implement Display different image content on the screen through the HDMI. 13.3 Experiment 13.3.1 Introduction to HDMI and ADV7511 Chip Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. HDMI (High Definition Multimedia Interface) is a digital video/audio interface…

FII-PRA040

FII-PRA040 User Experimental Manuals ( 2020-09-28 Updated )

September 28, 2020September 30, 2020 SteveGuysAudio Bus Protocol, WM8978 Control Interface Timing

PRA040 USER EXPERIMENTAL MANUAL PRA040 EXPERIMENTAL INSTRUCTIONS FRASER INNOVATION INC December 07, 2019 Version Control Version Date Description 1.0 07/20/2019 Initial Release 1.1 07/29/2019 Add Experiment 15 1.2 07/31/2019 Revised some description about HDMI 1.3 08/16/2019 SRAM part revised 1.4 08/30/2019 Add a description in Ethernet 1.5 09/17/2019 Revise some syntax and code error 1.6 12/06/2019 Add Experiments 16-19 Contents Project Files Appendix 9 Part One: Introduction of FII-PRA040 Development System 10 1、Design Objective of the System 10 2、System Resource 10 3、Human-computer Interaction Interface 10 4、Software Development System 11…

Signal waveform of AD9226 captured by logic analyzer

FII-PRX100-S FII-PRX100D PRX100

FII-PRX100T User Experiment Manuals （newly updated 2020-09-28)

September 28, 2020September 28, 2020 SteveGuys

PRX100 USER experimental manual PRX100 EXPERIMENTAL INSTRUCTIONS FRASER INNOVATION INC December 11, 2019 Version Control Version Date Descrption V1.0 07/10/2019 Initial Release V1.1 09/16/2019 Modify part of pin assignments and Ethernet description V1.2 12/12/2019 Add Experiments 15-20 Contents: Part 1 FII-PRX100 Development System Introduction 6 1. System Design Objective 6 2. System Resource 6 3. Human-computer Interaction Interface 6 4. Software Development System 7 5. Supporting Resources 7 Part 2 FII-PRX100 Main Hardware Resources Usage and FPGA Development Experiment 7 Experiment 1 LED Shifting 7 1. Experiment Object 7…

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FII-BD9361 RF Transceivers

FII-BD9361 (AD-FMCOMMS3-EBZ Board Compatible) Hardware Configuration

June 5, 2020October 31, 2020 SteveGuysFII-AD9361, Hardware Configuration

V1.0 Fraser innovation inc FII-BD9361 Hardware Reference Guide Version Control Version Date Description V1.0 12/03/2019 Initial Release Copyright Notice: © 2019 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how to use the product correctly. Improper…