Author: SteveGuys

Altera Risc-V FPGA Tutorial : Segment Display
Experimental Manuals FPGA Tutor Risc-V

Building FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II, Block/SCH – FII-PRA040 Risc-V FPGA Board Experimental 4

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Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3,…

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Atera Risc-V Segment Display Experimental
Experimental Manuals FPGA Tutor Risc-V

BCD code counter, Digital display decoding design, the serial FLASH of the development board : Segment Display – FII-PRA040 Risc-V FPGA Board Experimental 3

SteveGuys

Experiment 3 Segment Display 3.1 Experiment Objective Review experiment 1, proficient in PLL configuration, frequency division design, and project verification; Learn the BCD code counter; Digital display decoding design; Learn to download the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. The decimal point remains off and will not be considered for the time being. 3.3 Experiment 3.3.1 Introduction to the…

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Experimental Manuals FPGA Tutor Risc-V

SignalTap Logic Analyzer in Quartus, analyze the captured signals, – FII-PRA040 FPGA Board Experimental 2 – Risc-V FPGA Board Tutorial

SteveGuys

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice the use of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Use switches to control the LED light on and off and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction of DIP Switches and SignalTap Introduction of switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the circuit…

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Altera Risc-V FPGA Board
Experimental Manuals FII-PRA040 FII-PRX100-S FII-PRX100D FPGA Tutor Risc-V

use Quartus II to create projects，FPGA pin assignment， program downloading， writing of Verilog HDL programs， Altera Risc-V FPGA Tutorial : LED shifting – FII-PRA040 FPGA Board Experimental 1

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Experiment 1 LED shifting 1.1 Experiment Objective Practice to use Quartus II to create new projects and use system resources IP Core; Proficiency in the writing of Verilog HDL programs to develop a good code writing style; Master the design of the frequency divider to implemnet the runing LED; Combine hardware resources to perform FPGA pin assignment and implement actual program downloading; Observe the experiment result and summarize it. 1.2 Experiment Implement Use all LEDS, all light up during reset; End reset, LED lights from low to high (from right…

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Experimental Manuals FII-PRA040 FPGA Board Based Risc-V

SOPC (NiosII) system, simulation and verification of RISC-V CPU, Basic FPGA design training, IC design and verification – Altera Risc-V Board Tutorial : Introduction of FII-PRA040 Development System

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1、Design Objective of the System The main purpose of this system design is to complete FPGA learning, development and experiment with Intel Quartus. The main device uses the Inte Cyclone10 10CL040YF484C8G and is currently the latest generation of FPGA devices from Intel. The major learning and development projects can be completed as follows: Basic FPGA design training Construction and training of the SOPC (NiosII) system IC design and verification, the system provides hardware design, simulation and verification of RISC-V CPU Development and application based on RISC-V The system is specifically…

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HDMI connection block diagram
Experimental Manuals FPGA Tutor PRX100 Risc-V

Understand the register configuration of the ADV7511, HDMI Graphic Display Experiment – Xilinx Risc-V Board Tutorial : FII-PRX100 FPGA Board Experiment 14

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Experiment 14 HDMI Graphic Display Experiment 1.Experiment Objective Learn about video timing (2) Understand the register configuration of the ADV7511, reviewing the knowledge from experiment 12 2.Experiment Requirement Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. Display the image using the HDMI interface of the development board. Download the program to the board for comparison. Introduction to HDMI:…

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AD, DA Experiment Results
Experimental Manuals FPGA Tutor PRX100 Risc-V

digital-to-analog conversion: DAC, analog-to-digital conversion: ADC – Xilinx Risc-V Board Tutorial : AD, DA Experiment – FII-PRX100 FPGA Board Experiment 13

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Experiment 13 AD, DA Experiment 1.Experiment Objective Since in the real world, all naturally occurring signals are analog signals, and all that are read and processed in actual engineering are digital signals. There is a process of mutual conversion between natural and industrial signals (digital-to-analog conversion: DAC, analog-to-digital conversion: ADC). The purpose of this experiment is twofold: Learning the theory of AD conversion Read the value of AD acquisition from PCF8591, and convert the value obtained into actual value, display it with segment decoders 2.Experiment Requirement Perform analog-to-digital conversion using…

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Demonstration of the develop board
Experimental Manuals FPGA Tutor PRX100 Risc-V

Learning the basic principles of the different IIC bus, mastering the IIC communication protocol, Xilinx Risc-V Board Tutorial : IIC Protocol Transmission – FII-PRX100 FPGA Board Experiment 12

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Experiment 12 IIC Protocol Transmission 1.Experiment Objective There is an IIC interface EEPROM chip 24LC02 in the test plate, capacity sized 2 kbit (256 bite). Since the data is not lost after the EEPROM is powered down, users can store some hardware setup data or user information. Learning the basic principles of the different IIC bus, mastering the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 2.Experiment Requirement Correctly write a number to any address in the EEPROM (this experiment writes to…

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ModelSim simulation waves sent by serial
Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Asynchronous Serial Port Design and Experiment – FII-PRX100 FPGA Board Experiment 11

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Experiment 11 Asynchronous Serial Port Design and Experiment 1.Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 2.Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start bit,…

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Risc-V Board - Dual_port RAM test result
Experimental Manuals FPGA Tutor PRX100 Risc-V

Xilinx Risc-V Board Tutorial : Use Dual_port RAM to Read and Write Frame Data – FII-PRX100 FPGA Board Experiment 10

SteveGuys,

Experiment 10 Use Dual_port RAM to Read and Write Frame Data 1.Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Observing the synchronization structure of synchronous clock frames using ILA Extended the use of dual-port RAM Design the use of three-stage state machine 2.Experiment Requirement Generate dual-port RAM and PLL 16-bit width, 256-depth dual-port RAM 2 PLL, both 50 MHz input, different 100 MHz and 20…

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