Pocket Boards

Understand What Ethernet is and How it Works, the Relationship Between Different Interface Types (MII, GMII, RGMII) , Ethernet Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 14

November 17, 2020December 3, 2020 SteveGuysEthernet, Ethernet Experiment, GMII, Relationship Between Different Interface Types (MII, RGMII

Experiment 14 Ethernet Experiment 14.1 Experiment Objective Understand what Ethernet is and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (the development board uses RGMII) Combine the development board to complete the transmission and reception of data and verify it 14.2 Experiment Implement Perform a loopback test to check if the hardware is working properly. Performing data verification Perform data transmission verification 14.3 Experiment 14.3.1 Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method…

FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Reading and Writing EEPROM, the Basic Principles of Asynchronous IIC Bus, the IIC Communication Protocol, IIC transmitting Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 11

November 17, 2020February 24, 2021 SteveGuysIIC transmitting Experiment, Reading and Writing EEPROM, the IIC Communication Protocol

Experiment 11 IIC transmitting Experiment 11.1 Experiment Objective Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 11.2 Experiment Implement Correctly write a number to any address in the EEPROM (this experiment writes to the register of 8’h03 address) through the FPGA (here changes the written 8-bit data value by (SW7~SW0)). After writing in successfully, read the data as well. The read data is displayed directly on the segment display. Program the FPGA…

Experimental Manuals FPGA for Beginners Pocket Boards PRA006/PRA010

Asynchronous Serial Port Communication, Handshake Mechanism and Data Frame Strcuture, Asynchronous Serial Port Design and Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 10

November 17, 2020December 18, 2020 SteveGuysAsynchronous serial port communication, Asynchronous Serial Port Design, Handshake Mechanism and Data Frame Strcuture

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Study the basic principles of asynchronous serial port communication, handshake mechanism and data frame strcuture Master asynchronous sampling techniques Review the frame structure of the data packet Learn to use FIFO Joint debugging with common debugging software of PC (SSCOM, Tera Term, etc.) 10.2 Experiment Implement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of…

Experimental Manuals FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Configure and Use Dual-port RAM, Use Dual_port RAM to Read and Write Frame Data – FPGA Beginner Study Board PRA006, PRA010 Experiment 9

November 17, 2020December 15, 2020 SteveGuysDual-port RAM, FPGA Beginner Study Board, PRA006, PRA010, Read and Write Frame Data

Experiment 9 Use Dual_port RAM to Read and Write Frame Data 9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Experiment Implement Observing the synchronization structure of synchronous clock frames using SignalTap II Extended the use of dual-port RAM Design the use of three-stage state machine Design a 16-bit data frame Data is generated by an 8-bit counter: Data={~counta,counta} The ID of the data frame…

Experimental Manuals FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Study the Format of .mif File and How to Edit .mif File ，Study the Internal Memory Block of FPGA，Use of ROM – FPGA Beginner Study Board PRA006, PRA010 Experiment 8

November 16, 2020December 3, 2020 SteveGuysFPGA Beginner Study Board, How to Edit *.mif File, PRA006, PRA010, the Format of *.mif File, the Internal Memory Block of FPGA, Use of ROM

Experiment 8 Use of ROM 8.1 Experiment Objective Study the internal memory block of FPGA Study the format of *.mif and how to edit *.mif file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Implement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment display illustrates the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Introduction to Program This experiment was carried out on the basis of Experiment 7, and…

Experimental Manuals FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

FPGA for Beginner Board Experimental Manuals and Study Guide – PRA006, PRA010 FPGA Beginner Study Board

November 12, 2020December 3, 2020 beginner FPGA

Fraser Innovation Inc FII-PRA006/010 User Experimental Manual Version Control Version Date Descrption V1.0 10/07/2019 Initial Release V1.1 12/07/2019 Add figures for corresponding experimental phonomena of experiment board V1.2 30/08/2019 Modify part of pin assignments and Ethernet description Project Files Content Experiment 1: LED_shifting Experiment 2: SW_LED Experiment 3: BCD_counter Experiment 4: block_counter Experiment 5: block_debouncing Experiment 6: mult_sim Experiment 7: HEX_BCD, HEX_BCD_mult Experiment 8: memory_rom Experiment 9: dual_port_ram Experiment 10: UART_FRAME Experiment 11: eeprom_test Experiment 12: adda_test Experiment 13: vga Experiment 14: Ethernet Part One: Introduction to FII-PRA006/010…

Configuration Pocket Boards

JTAG Configuration Description – FII-PRA010 – Cyclone-10 FPGA Development Board with Jtag Embeded

July 26, 2019September 25, 2019 SteveGuys

FII-PRA010 – Cyclone-10 FPGA Development Board is based on our FII-PRA010 fpga board. You can buy it only $59. The official shopping website: https://fpgamarketing.com/FPGA-Study-Board-Verilog-for-beginner-Cyclone-10-FII-PRA006-FII-PRA006.htm Altera FPGA Study Board, Verilog for beginner – Cyclone-10 FPGA Development Board with Jtag Embeded – FII-PRA006 The advantage of FPGA beginner board: Beginner FPGA study board, cheaper but fully functional. cellphone sized. ( < 100 USD ) power supply and download at the same time, no extra power supply and no extra data transfer line needed Small volume and light and can be put into…

Configuration Pocket Boards

JTAG Configuration Description – FII-PRA006 – Cyclone-10 FPGA Development Board with Jtag Embeded

July 26, 2019July 26, 2019 SteveGuys

The latest DLL versions for Altera Quartus II or Intel Quartus Prime are 1.8b (Provided in the folder), for Quartus in Linux, get version 1.7b. To install the driver for Quartus II, do the following: Connect the MBFTDI programmer with a USB cable to a Windows computer. Make sure the device is detected and the FTDI drivers are already installed. To do this, look in the Device Manager Windows, in the COM and LPT ports section, two COM ports should appear. If instead you find two yellow question marks, then you need…

FPGA for Beginners FPGA Tutor Pocket Boards

FPGA Tutorial – Asynchronous Serial Port Design and Experiment – FPGA for Beginner – Experiment 10

July 22, 2019February 24, 2021 SteveGuysAsynchronous Serial Port Design

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Learning the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Requirement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1…