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FPGA Tutorial – Use Multiplier and ModelSim – FPGA Board for Beginner – Experiment 6

6.1 Experiment Objective

  1. Learn to use multiplier
  2. Use ModelSim to output

6.2 Experiment Requirement

  1. 8×8 multiplier. The first input is 8-bit switch, and the second input is the output of an 8-bit counter.

  2. Observe the output in ModelSim.

  3. Observe the calculation result on 4 segment decoders.

6.3 Experiment

  1. Build a new project mult_sim

Different from what we did before, we use EDA simulation. The actual setting is shown in Fig 6. 1

Set EDA tool
Set EDA tool
  1. Design procedure
    1. Create a new file named mult_sim.v

    2. Add PLL, set the clock input frequency is 50 MHz, and the output is 100 MHz

    3. In the right of the main interface, find Installed IP > Library > Basic Functions > Arithmetic > LPM_MULT IP. An interface will pop up. See Fig 6. 2

  1. LPM_MULT_interface
    LPM_MULT_interface
    1. Select the Multiplication Type to be unsigned. See Fig 6. 3

      Multiplication type selection
      Multiplication type selection

    1. In Pipelining, select Yes, and set the output latency to be 1 clock cycle. Pipeline will speed up the execution speed. See Fig 6. 4
    2. Make other settings default.
    3. Instantiate it in the top level file.

      Pipelining setting
      Pipelining setting

 

  1. The top level file is as follows
module mult_sim (
	input				inclk,
	input				rst,
	input		[7:0]	sw,
	output		[6:0]	seven_seg,
	output		[3:0]	scan,
	output		[15:0]	mult_res,
	output	reg	[7:0]	count
);

	wire			sys_clk;
	wire			sys_rst;
	
	always @ (posedge sys_clk)
		if(sys_rst)
			count <= 0;
		else
			count <= count + 1;
	
	pll_sys_rst pll_sys_rst_inst(
			.inclk		(inclk),
			.sys_clk	(sys_clk),
			.sys_rst	(sys_rst)
		);

	mult_8x8 mult_8x8_inst (
			.clock (sys_clk),
			.dataa (sw),
			.datab (count),
			.result (mult_res)
		);
endmodule

  • ModelSim simulation

  1. Simulation based on waveform inputs

  2. Tool > Option. In the popup window, under General, find EDA Tool Options. In ModelSim-Altera, find the correct path. See Fig 6. 5

Fig 6. 5 Set the correct path for ModelSim-Altera

  1. Tool > Run Simulation Tool > RTL Simulation. See Fig 6. 6

Fig 6. 6 Simulation interface

  1. Set ModelSim
  1. Simulate > Start Simulation
  2. In the popup window, add libraries under Libraries tag. See Fig 6. 7
  3. Under Design tag, choose simulation project mult_sim and click OK. See Fig 6. 8

Fig 6. 7 Add simulation libraries

Fig 6. 8 Choose the project in simulation

  1. In the Objects window, choose all the signals and drag them to Wave window. See Fig 6. 9

Fig 6. 9 Add observation signals

  1. Set the signals in Wave, right click any signal and a selection window will occur. See Fig 6. 10

Fig 6. 10 Set the signals

  1. For logical signals select Force and select Clock for clock signals
  1. Set rst signal. See Fig 6. 11

Fig 6. 11 Set rst signal

  1. Set Inclk signal. See Fig 6. 12

Fig 6. 12 Set inclk signal

  1. Set sw signal. See Fig 6. 13

Fig 6. 13 Set sw signal

  1. Run simulation. In the tool bar, set the simulation time to be 100 ns. Click the Run icon to run. See Fig 6. 14

Fig 6. 14 Set the simulation time

  1. Observe the simulation result. See Fig 6. 15

Fig 6. 15 Simulation result

  1. Result analysis

  1. Counter count does not have a valid result, instead, unknow result XXXXXX is gotten.

  2. sys_rst does not reset signals. It changes from X to 0

  3. Add pll_locked signal to the wave, and re-simulate

Fig 6. 16 Re-simulation result

  1. In Fig 6. 16, before PLL starts to lock, the sys_clk already has a rising edge, so PLL_locked signal is just converted from low to high. There is no reliable reset is formed.

  2. Solution

Method 1: Define sys_rst to be 1’b0

module pll_sys_rst(

input inclk,

output sys_clk,

output reg sys_rst =1’b1

);

Method 2: Use external rst signal to procide reset

Here, method 1 is adopted

Fig 6. 17 Recompile the simulation

  1. Recompile the simulation. See Fig 6. 17
  2. Since waveform editing efficiency is relatively low, the use of simulation testbench file is encouraged. Name a new Verilog HDL file tb_mult.v.

`timescale 10ns/1ns

module tb_mult; //Define the simulation signal

reg rst;

reg clk;

reg [7:0] sw;

wire [7:0] count;

wire [7:0] seven_seg;

wire [3:0] scan;

wire [15:0] mult_res;

mult_sim S1( // S1 is the instance of simulation module

.rst (rst),

.inclk (clk),

.sw (sw),

.seven_seg (seven_seg),

.scan (scan),

.count (count),

.mult_res (mult_res)

);

always #5 clk = ~clk;

initial //Initialize the simulation signals

begin

rst = 0;

clk = 1;

#5 sw = 20;

#10 sw = 50;

#10 sw = 100;

#10 sw = 101;

#10 sw = 102;

#10 sw = 103;

#10 sw = 104;

#50 sw = 105;

$monitor(“%d * %d=%d”, count, sw, mult_res);

#1000 $stop;

end

endmodule

  1. Compile and simulate
  1. Only choose Start Analysis & Elaboration, do not choose either compilation or synthesis one. See Fig 6. 18

Fig 6. 18 TB file analyzing

  1. Set the testbench file: Assignments > Settings. See Fig 6. 19

Fig 6. 19 Simulation setting 1

Go to Simulation, For Tool name, select ModelSim-Altera. In Compile test bench, click Test Benches to add tb simulation file. See Fig 6. 20

Fig 6. 20 Simulation setting 2

Click New, input the Test bench name. Make the name be consistent with tb file. See Fig 6. 21.

Fig 6. 21 Simulation setting 3

Click the red ellipse to add the test bench file. Find tb_mult.v file written before. Click Add to add. Click OK (three times) to finish the setting. See Fig 6. 22

Fig 6. 22 Simulation setting 4

  1. Repeat previous step, to start ModelSim to simulate. See Fig 6. 23

Fig 6. 23 Waveform output

  1. After a certain delay, outputs will display in Transcript. See Fig 6. 24

Fig 6. 24 Text displays operation result

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