SteveGuys | Fraser Innovation Inc

xc7z030 board hardware resources and block diagram of ZYNQ chip

March 2, 2020June 2, 2020 SteveGuysBasic Features, FPGA, JTAG interfaces, PE7030, xc7z030 board

This development board uses Xilinx’s zynq7000 series chip, model XC7Z030-2FFG676I, 676-pin FPGA package. This chip can be divided into a PS (Processor System) part and a PL (Programmable Logic) part. On the PE7030 development board, the PS and PL sections of the XC7Z030 are both equipped with a wealth of external interfaces and devices for convenience use and functional verification. In addition, as always, the USB Cable downloader circuit is integrated on the development board. Users only need to use a USB cable to download and debug the development board.…

FPGA for Beginners

What is the main components of the FRA006 FPGA beginner board with JTAG downloader ?

February 24, 2020August 22, 2020 SteveGuysbeginner board, FPGA beginner board, JTAG downloader, main components

What is the main components of the FRA006 FPGA beginner board ? What is the main components of the FRA006 FPGA beginner board ? 10CL006YE144C8G or 10CL006YE144C8G 6-digit common anode seven-segment display USB power supply and download interface External expansion interface GPIO 8 DIP switches 8 LEDs USB to serial port chip (FT2232)(Intefrated JTAG download function) 50 MHz oscillator Thermistor (NTC-MF52) Potentiometer Photoresistor 4 buttons (up, down, right, down) Reset button (Reset) JTAG downloader function conversion interface JTAG download interface (Used only when the board is used as a downloader)…

FPGA Board Based RF Transceivers USRP

What is the features and benefits of your FII-BD9361 (AD-FMCOMMS3-EBZ compatible ) boards ?

February 23, 2020March 2, 2021 SteveGuysAD-FMCOMMS3-EBZ, FII-PE7030, ZC702, ZC706, Zedboard

What is the FII-BD9361 Features: We support all features of AD-FMCOMMS3-EBZ such as: TX band: 47 MHz to 6.0 GHz RX band: 70 MHz to 6.0 GHz Bandwidth Adjustment Range: 200 kHz to 56 MHz Low noise figure: 2dB NF（noise figure/800MHz ) LO ,RX Gain Control，AGC 2.4Hhz local oscillator (LO) step For more information, please check ad9361 introduction. What is the benefits of AD-FMCOMMS3-EBZ ( Compatible with FII-BD9361) Software tunable across wide frequency range : TX :47 MHz to 6 GHz RX:70 MHz to 6 GHz Software tunable bandwidth: 200…

Ethernet Experiment Information received by PC from FPGA

FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

Ethernet work mechanism, the relationship between different interface types (MII, GMII, RGMII), leanrn how to transmission and reception of data, zynq xc7z030 board – FII-PE7030 Experiment 13

January 7, 2020February 1, 2021 SteveGuysEthernet Experiment, Experiment, FII-PE7030, zynq xc7z030 board

Experiment 13 Ethernet 13.1 Experiment Objective Understand what Ethernet and how it works Familiar with the relationship between different interface types (MII, GMII, RGMII) and their advantages and disadvantages (here uses RGMII) Combine the development board to complete the transmission and reception of data and verify it 13.2 Experiment Implement Perform a loopback test to check if the hardware is working properly. Perform data receiving verification Perform data transmission verification 13.3 Experiment 13.3.1 Introduction to Experiment Principle Ethernet is a baseband LAN technology. Ethernet communication is a communication method that…

zynq xc7z030 board – FII-PE7030 Experiment 12 - HDMI display (color strip)

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

IIC protocol knowledge，Learn HDMI theory – zynq xc7z030 board – FII-PE7030 Experiment 12 – HDMI Experiment

January 7, 2020September 8, 2020 SteveGuysExperiment, FII-PE7030, HDMI display, HDMI Experiment, zynq xc7z030 board

Experiment 12 HDMI Experiment 12.1 Experiment Objective Review IIC protocol knowledge Learn HDMI theory 12.2 Experiment Implement Through the HDMI interface, different image contents are displayed on the screen. 12.3 Experiment 12.3.1 Introduction to HDMI Interface and ADV7511 Chip Image display processing has always been the focus of FPGA research. At present, the image display mode is also developing. The image display interface is also gradually transitioning from the old VGA interface to the new DVI or HDMI interface. HDMI (High Definition Multimedia Interface) is a digital video/audio interface technology.…

IIC transmission experimental phenomenon

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

asynchronous IIC bus, and the IIC communication protocol， reading and writing EEPROM – zynq xc7z030 board – FII-PE7030 Experiment 11 – IIC Protocol Transmission

January 7, 2020September 8, 2020 SteveGuysExperiment, FII-PE7030, IIC Protocol Transmission, zynq xc7z030 board

Experiment 11 IIC Protocol Transmission 11.1 Experiment Objective Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 11.2 Experiment Implement Correctly write a number to any address in the EEPROM (this experiment writes to the register of 8’h03 address) through the FPGA (here changes the written 8-bit data value by (SW7~SW0)). After writing in successfully, read the data as well. The read data is displayed directly on the segment display. Download the program…

zynq xc7z030 board – FII-PE7030 Experiment 10 -Sent data received on the host computer

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

zynq xc7z030 board – FII-PE7030 Experiment 10 – Asynchronous Serial Port Design and Experiment

January 7, 2020 SteveGuysAsynchronous Serial Port Design and Experiment, FII-PE7030, FPGA development, zynq xc7z030 board

10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. Study the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Implement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start bit, 1 or 2 stop bits Receive…

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

zynq xc7z030 board – FII-PE7030 Experiment 9 – Use Dual-port RAM to Read and Write Frame Data

January 7, 2020 SteveGuysDual-port RAM, Experiment, FII-PE7030, Frame Data, Use Dual-port RAM to Read and Write Frame Data, zynq xc7z030 board

Experiment 9 Use Dual-port RAM to Read and Write Frame Data 9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Use ILA to observe the structure of a synchronized clock frame Extended the use of dual-port RAM Design the use of three-stage state machine Experiment Implement Use ILA to observe the structure of a synchronized clock frame Extended the use of dual-port RAM Design the…

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

zynq xc7z030 board – FII-PE7030 Experiment 8 – Use of ROM, Study the format of .coe and how to edit .coe file to configure the contents of ROM

January 7, 2020August 24, 2020 SteveGuysbitstream, Experiment, FII-PE7030, Use of ROM, zynq xc7z030 board

Experiment 8 Use of ROM 8.1 Experiment Objective Study the usage of internal memory block of FPGA Study the format of *.coe and how to edit *.coe file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Implement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment display illustartes the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Program Design The first step: the establishment of the main program…

Experimental phenomenon of hexadecimal number to BCD code conversion

Experimental Manuals FII-PE7030 FPGA Products

Binary numbers to BCD (bin_to_bcd), Hexadecimal Number to BCD (hex_to_bcd) Code Conversion and Application – zynq xc7z030 board – FII-PE7030 Experiment 7

January 7, 2020June 28, 2020 SteveGuysBCD Code, bitstream file, FII-PE7030, Hexadecimal Number, zynq xc7z030 board

Experiment 7 Hexadecimal Number to BCD Code Conversion and Application Experiment Objective Learn to convert binary numbers to BCD (bin_to_bcd) Learn to convert hexadecimal numbers to BCD (hex_to_bcd) 7.2 Experiment Implement Combined with experiment 6, display the calculation results on the segment display. 7.3 Experiment 7.2.1 Introduction to Hexadecimal Number to BCD Code Conversion Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eye recognition is relatively slow, so the display from hexadecimal to decimal does not need to be too fast.…