FPGA Board Based

AD9371

December 10, 2020April 9, 2021 beginner FPGAad9361, ad9361 development board, ad9371, AD9371 Evaluation Boards, AD9371 RF transceiver, algorithms, Filter and Signal Path Configuration, RX Signal Path

ADRV9371-W/PCBZ Compatible RF/IF and RFID FPGA Board -$999 – AD9371 Development Board- FII-BD9371 Board AD9371 Evaluation Boards AD9371 Overview The AD9371 RF transceiver is designed for applications that require high performance radio transmissions across a wideband frequency range, such as 3G/4G Macro BTS, 3G/4G Massive MIMO, and SDR. The AD9371 is packaged in a highly integrated 12mm x 12mm SoC which replaces as many as 20 high performance discrete components. Introducing the AD9371 The AD9371 RF transceiver is for applications that require high performance radios across a wideband frequency range…

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V

Combined With the BCD_Counter Project to Achieve the Display of the Digital Clock, Master the Design Method of Graphics From Top to Bottom – Block/SCH – Altera Risc-V Board PRA040 Experimental 4

November 18, 2020December 17, 2020 SteveGuysAchieve the Display of the Digital Clock, Altera Risc-V Board PRA040, BCD_Counter Project, Block/SCH, Experimental, Master the Design Method of Graphics From Top to Bottom

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3…

Experimental Manuals FII-PRA040 FPGA Board Based FPGA Tutor Risc-V Risc-V Core

Frequency Division Design, Learn the BCD Code Counter, Digital Display Decoding Design, Segment Display – Altera Risc-V Board PRA040 Experimental 3

November 18, 2020February 1, 2021 SteveGuysAltera Risc-V Board, Digital Display Decoding Design, Frequency Division Design, Learn the BCD Code Counter, PRA040, segment display

Experiment 3 Segment Display 3.1 Experiment Objective Review experiment 1, proficient in PLL configuration, frequency division design, and project verification; Learn the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. The decimal point remains off and will not be considered for the time being. 3.3 Experiment 3.3.1 Introduction to the…

FPGA Board Based FPGA for Beginners FPGA Tutor Pocket Boards PRA006/PRA010

Reading and Writing EEPROM, the Basic Principles of Asynchronous IIC Bus, the IIC Communication Protocol, IIC transmitting Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 11

November 17, 2020February 24, 2021 SteveGuysIIC transmitting Experiment, Reading and Writing EEPROM, the IIC Communication Protocol

Experiment 11 IIC transmitting Experiment 11.1 Experiment Objective Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 11.2 Experiment Implement Correctly write a number to any address in the EEPROM (this experiment writes to the register of 8’h03 address) through the FPGA (here changes the written 8-bit data value by (SW7~SW0)). After writing in successfully, read the data as well. The read data is displayed directly on the segment display. Program the FPGA…

Experimental Manuals FPGA Board Based FPGA for Beginners PRA006/PRA010

Binary Numbers or Hexadecimal Number to BCD Code Conversion and Application – FPGA Beginner Study Board PRA006, PRA010 Experiment 7

November 16, 2020February 23, 2021 SteveGuysBCD Code, Binary Numbers, FPGA Beginner Study Board, Hexadecimal Number, PRA006, PRA010

Experiment 7 Hexadecimal Number to BCD Code Conversion and Application Experiment Objective Learn to convert binary numbers to BCD code (bin_to_bcd) Learn to convert hexadecimal numbers to BCD code (hex_to_bcd) 7.2 Experiment Implement Combined with experiment 6, display the results of the operation to the segment display. 7.3 Experiment 7.2.1 Introduction to the Principle of Converting Hexadecimal Number to BCD Code Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eyes recognition is relatively slow, so the display from hexadecimal to decimal…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

Button Debounce Principle and Adaptive Programming – Button Debounce Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 5

November 16, 2020 SteveGuysAdaptive Programming, Button Debounce, Button Debounce Experiment, Button debounce experiment phenomenon, button debounce principle, FPGA Beginner Study Board, PRA006, PRA010

Experiment 5 Button Debounce Experiment 5.1 Experiment Objective Review the design process of the shifting LED Learn button debounce principle and adaptive programming Study the connection and use of the FII-PRA006/010 button hardware circuit Comprehensive application button debounce and other conforming programming 5.2 Experiment Implement Control the movement of the lit LED by pressing the button Each time the button is pressed, the lit LED moves one bit. When the left shift button is pressed, the lit LED moves to the left, presses the right button, and the lit LED…

Experimental Manuals FPGA Board Based FPGA for Beginners PRA006/PRA010

Building new FPGA Projects in Quartus, Device Selection, PLL setup, PLL Frequency Setting, Verilog’s Tree Hierarchy Design, and the Use of SignalTap II – Block/SCH Experiment – FPGA Beginner Study Board PRA006, PRA010 Experiment 4

November 16, 2020February 24, 2021 SteveGuysBlock/SCH Experiment, device selection, FPGA Beginner Study Board, PLL frequency setting, PLL setup, PRA010, Quartus, SignalTap II, Verilog's Tree Hierarchy Design

Experiment 4 Block/SCH Experiment 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL setup, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

Use the BCD Code Counter, Digital Display Decoding Design, the Serial Flash, – Segment Display – FPGA Beginner Study Board PRA006, PRA010 Experiment 3

November 16, 2020March 2, 2021 SteveGuysBCD Code Counter, Digital Display Decoding Design, FPGA Beginner Study Board, PRA006, PRA010 Experiment 3, segment display, the Serial Flash

Experiment 3 Segment Display 3.1 Experiment Objective Review previous experiments, proficient practice in PLL configuration, frequency division design, and project verification; Learn to use the BCD code counter; Digital display decoding design; Learn to program the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower (right most) digits to display seconds, the middle two digits to display minutes, and the highest (left most) two digits to display hours. The decimal point remains off and will not be considered for the time…

Experimental Manuals FPGA Board Based FPGA for Beginners FPGA Tutor PRA006/PRA010

The Use of SignalTap Logic Analyzer, Analyze the Captured Signals – FPGA Beginner Study Board PRA006, PRA010 Experiment 2

November 16, 2020January 6, 2021 SteveGuysAnalyze the Captured Signals, FPGA Beginner, Logic Analyzer, PRA006, PRA010, SignalTap, Study Board

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice using of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Capture and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction to the Switches and SignalTap Introduction to the switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the circuit by turning the switch handle using the binary coding…

FII RISC-V3.01 CPU FII-PRX100-S FII-PRX100D FPGA Board Based FPGA Tutor PRX100 Risc-V Risc-V Core Risc-V Tutorial

C Programming (1) on RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board with our FII-Risc-V CPU (RV32G2.0)

November 9, 2020November 9, 2020 beginner FPGA32 registers, ARTIX-7, C Project Compilation Process, CPU, FII-PRX100, FII-RISCV CPU, Freedom Studio, Linker functionality, XC7A100T, XILINX FPGA Board

V1.0 Fraser Innovation inc RISCV FII-PRX100 (ARTIX-7, XC7A100T) XILINX FPGA Board C Programming 1 Version Control Version Date Description 1.0 10/24/2020 Initial Release Copyright Notice: © 2020 Fraser Innovation Inc ALL RIGHTS RESERVED Without written permission of Fraser Innovation Inc, no unit or individual may extract or modify part of or all the contents of this manual. Offenders will be held liable for their legal responsibility. Thank you for purchasing the FPGA development board. Please read the manual carefully before using the product and make sure that you know how…