Risc-V - Part 4

Asynchronous serial port communication, handshake mechanism, data frame, Asynchronous Serial Port Design and Experiment – FII-PRA040 Risc-V FPGA Board Experimental 10

Asynchronous serial port communication, Asynchronous Serial Port Design, data frame, FIFO, handshake mechanism, SSCOM, teraterm

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Implement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start…

Experimental Manuals FPGA Tutor Risc-V

Altera Risc-V FPGA Tutorial : Use Dual-port RAM to Read and Write Frame Data – FII-PRA040 FPGA Board Experimental 9

Experiment 9 Use Dual-port RAM to Read and Write Frame Data 9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Experiment Implement Observing the synchronization structure of synchronous clock frames using SignalTap II Extended the use of dual-port RAM Design the use of three-stage state machine Design a 16-bit data frame Data is generated by an 8-bit counter: Data={~counta,counta} The ID of the data frame…

Experimental Manuals FPGA Tutor Risc-V

Altera Risc-V FPGA Tutorial : Use of ROM – Study the format of .mif and how to edit .mif file，Learn to use RAM, read and write RAM， FII-PRA040 FPGA Board Experimental 8

internal memory block, Use of ROM

Experiment 8 Use of ROM 8.1 Experiment Objective Study the internal memory block of FPGA Study the format of *.mif and how to edit *.mif file to configure the contents of ROM Learn to use RAM, read and write RAM 8.2 Experiment Implement Design 16 outputs ROM, address ranging 0-255 Interface 8-bit switch input as ROM’s address Segment display the contents of ROM and require conversion of hexadecimal to BCD output. 8.3 Experiment 8.3.1 Introduction of the Program This experiment was carried out on the basis of Experiment 7, and…

Altera Risc-V FPGA Tutorial : Hexadecimal Number to BCD Code Conversion and Application Experimental

Experimental Manuals FPGA Tutor Risc-V

Altera Risc-V FPGA Tutorial : Hexadecimal Number to BCD Code Conversion and Application – FII-PRA040 FPGA Board Experimental 7

Experiment 7 Hexadecimal Number to BCD Code Conversion and Application Experiment Objective Learn to convert binary numbers to BCD code (bin_to_bcd) Learn to convert hexadecimal numbers to BCD code (hex_to_bcd) 7.2 Experimental Implement Combined with experiment 6, display the results of the operation to the segment display. 7.3 Experiment 7.2.1 Introduction to the principle of hexadecimal number to BCD code Since the hexadecimal display is not intuitive, decimal display is more widely used in real life. Human eyes recognition is relatively slow, so the display from hexadecimal to decimal does…

Experimental Manuals FPGA Tutor Risc-V

Use multiplier, Use ModelSim to simulate design output, Use of Multipliers and ModelSim – FII-PRA040 Altera Risc-V FPGA Board Experimental 6

Use ModelSim to simulate design output, Use multiplier, Use of Multipliers and ModelSim

Experiment 6 Use of Multipliers and ModelSim 6.1 Experiment Objective Learn to use multiplier Use ModelSim to simulate design output 6.2 Experiment Implement 8×8 multiplier, the first input value is an 8-bit switch, and the second input value is the output of an 8-bit counter. Observe the output in ModelSim Observe the calculation results with a four-digit segment display 6.3 Experiment Since learning uses of the simulation tools and the new IP core, there is no introduction and hardware design part. 6.3.1 Introduction of Program ModelSim is an HDL language…

Experimental Manuals FII-PRA040 FPGA Tutor Risc-V

The design process of the shifting LED, debounce principle and adaptive programming, button hardware circuit, Button Debounce Programming – FII-PRA040 Risc-V FPGA Board Experimental 5

Button Debounce Programming, button hardware circuit, debounce principle and adaptive programming, The design process of the shifting LED

Experiment 5 Button Debounce 5.1 Experiment Objective Review the design process of the shifting LED Learn button debounce principle and adaptive programming the connection and use of the Fii-PRA040 button hardware circuit Comprehensive application button debounce and other conforming programming 5.2 Experiment Implement Control the movement of the lit LED by pressing the button Each time the button is pressed, the lit LED moves one bit. When the left shift button is pressed, the water lamp moves to the left, presses the right button, and the water lamp moves to…

Altera Risc-V FPGA Tutorial : Segment Display

Experimental Manuals FPGA Tutor Risc-V

Building FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II, Block/SCH – FII-PRA040 Risc-V FPGA Board Experimental 4

device selection, FII-PRA040, FPGA projects, PLL creation, PLL frequency setting, Quartus, SignalTap II, Verilog tree hierarchy

Experiment 4 Block/SCH 4.1 Experiment Objective Review building new FPGA projects in Quartus, device selection, PLL creation, PLL frequency setting, Verilog’s tree hierarchy design, and the use of SignalTap II Master the design method of graphics from top to bottom Combined with the BCD_counter project to achieve the display of the digital clock Observe the experimental results 4.2 Experiment Implement Use schematics design to build the project. 4.3 Experiment This experiment is mainly to master another design method. The other design contents are basically the same as the experiment 3,…

Atera Risc-V Segment Display Experimental

Experimental Manuals FPGA Tutor Risc-V

BCD code counter, Digital display decoding design, the serial FLASH of the development board : Segment Display – FII-PRA040 Risc-V FPGA Board Experimental 3

Experiment 3 Segment Display 3.1 Experiment Objective Review experiment 1, proficient in PLL configuration, frequency division design, and project verification; Learn the BCD code counter; Digital display decoding design; Learn to download the project into the serial FLASH of the development board; 3.2 Experiment Implement The segment display has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. The decimal point remains off and will not be considered for the time being. 3.3 Experiment 3.3.1 Introduction to the…

Experimental Manuals FPGA Tutor Risc-V

SignalTap Logic Analyzer in Quartus, analyze the captured signals, – FII-PRA040 FPGA Board Experimental 2 – Risc-V FPGA Board Tutorial

Experiment 2 SignalTap 2.1 Experiment Objective Continue to practice the use of the development board hardware; Practice the use of SignalTap Logic Analyzer in Quartus; Learn to analyze the captured signals. 2.2 Experiment Implement Use switches to control the LED light on and off and analyze the switching signals on the development board through the use of SignalTap. 2.3 Experiment 2.3.1 Introduction of DIP Switches and SignalTap Introduction of switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the circuit…

Experimental Manuals FII-PRA040 FII-PRX100-S FII-PRX100D FPGA Tutor Risc-V

use Quartus II to create projects，FPGA pin assignment， program downloading， writing of Verilog HDL programs， Altera Risc-V FPGA Tutorial : LED shifting – FII-PRA040 FPGA Board Experimental 1

LED physical picture, Quartus, The schematics of LED, Verilog HDL

Experiment 1 LED shifting 1.1 Experiment Objective Practice to use Quartus II to create new projects and use system resources IP Core; Proficiency in the writing of Verilog HDL programs to develop a good code writing style; Master the design of the frequency divider to implemnet the runing LED; Combine hardware resources to perform FPGA pin assignment and implement actual program downloading; Observe the experiment result and summarize it. 1.2 Experiment Implement Use all LEDS, all light up during reset; End reset, LED lights from low to high (from right…