Experimental Manuals

BCD decoder, Display design of hexadecimal to 7 segment display decoders, Achieve digital clock display – zynq xc7z030 board – FII-PE7030 Experiment 3 – Segment Display Digital Clock Experiment

Achieve digital clock display, BCD decoder, bitstream files, Display design of hexadecimal to 7 segment display decoders, FII-PE7030, pin assignment of FPGA, the design of frequency divider, Verilog tree hierarchy, zynq xc7z030 board, Zynq_7030 development board

3.1 Experiment Objective Review the contents of experiment 1 and experiment 2, master the configuration of PLL, the design of frequency divider, the principle of schematics and the pin assignment of FPGA. Familiar with the design of Verilog’s tree hierarchy Study BCD decoder Display design of hexadecimal to 7 segment display decoders Achieve digital clock display 3.2 Experiment Implement The display decoder has two lower digits to display seconds, the middle two digits to display minutes, and the highest two digits to display hours. Separate the seconds, minutes, and hours…

Debugging results - Analysis of Switch Signals via ILA

Experimental Manuals FII-PE7030 FPGA Products

Learn to use ILA (Integrated Logic Analyzer) in Vivado, Practice the call of system resource PLL, zynq xc7z030 board – FII-PE7030 Experiment 2

Integrated Logic Analyzer, Switch Signals, xc7z030 board, zynq xc7z030 board

Experiment 2 Analysis of Switch Signals via ILA 2.1 Experiment Objective Continue to practice using develop board Continue to practice the call of system resource PLL Learn to use ILA (Integrated Logic Analyzer) in Vivado 2.2 Experiment Implement Capture and analyze switch signals on the development board by using ILA 2.3 Experiment 2.3.1 Introduction of Switches The on-board switch is 8 DIP switches, as shown in Figure 2.1. The switch is used to switch the circuit by turning the switch handle. Figure 2.1 Switch physical picture 2.3.2 Hardware Design The…

Experimental Manuals FII-PE7030 FPGA Products Risc-V

zynq xc7z030 board – use Vivado to establish a new project, call the system resource PLL to establish the clock， Write Verilog HDL program to achieve frequency division and implement LED shifting，FII-PE7030 Experiment 1 LED Shifting Design

LED shifting, zynq xc7z030 board

Experiment 1 LED Shifting Design 1.1 Experiment Objective Practice how to use the development system software Vivado to establish a new project, call the system resource PLL to establish the clock. Write Verilog HDL program to achieve frequency division and implement LED shifting Combine hardware resources for FPGA pin configuration Compile, download the program to the develop board, and verify Observe the experimental result and debug the project 1.2 Experiment Implement All LEDs light up during reset; After reset, LED lights from low to high (from right to left) in…

Experimental Manuals FII-PE7030 FPGA Board Based FPGA Products FPGA Tutor

EVB Board – Basic FPGA design training – FII-PE7030 User Experimental Manuals

EVB Board, FIII-PE7030, xc7z030 ZYNQ

Version Control Version Date Description V1.0 21/11/2019 Initial Release Contents Part One: Introduction to Zynq_7030 Development System 5 1、System Design Objective 5 2、System Resource 5 3、Human-computer Interaction Interface 5 4、Software Development System 6 5、Supporting Resources 6 6、Physical Display 6 Part Two: zynq_7030 Main Resources Usage and FPGA Development Experiemnt 8 Experiment 1 LED Shifting Design 9 1.1 Experiment Objective 9 1.2 Experiment Implement 9 1.3 Experiment 9 1.3.1 LED Introduction 9 1.3.2 Hardware Design 9 1.3.3 Program Design 10 1.4 Experiment Verification 26 Experiment 2 Analysis of Switch Signals via…

Experimental Manuals FII-PRX100-S FII-PRX100D FPGA Products FPGA Tutor PRX100 Risc-V

RISC-V FPGA Board Study Guide – FII-PRX100 Experimental Manuals

AD, DA Experiment, HDMI display, HDMI Graphic Display Experiment

Version Control Version Date Descrption V1.0 10/07/2019 Initial Release V1.1 16/09/2019 Modify part of pin assignments and Ethernet description Contents: Part 1 FII-PRX100 Development System Introduction 5 1. System Design Objective 5 2. System Resource 5 3. Human-computer Interaction Interface 5 4. Software Development System 6 5. Supporting Resources 6 Part 2 FII-PRX100 Main Hardware Resources Usage and FPGA Development Experiment 6 Experiment 1 LED Shifting 6 1. Experiment Object 6 2. Create A New Project Under Vivado 6 Experiment 2 Switches and display 25 1.Experiment Objective 25 2.Start New…

FPGA Board For Beginner with free Experimental Manuals

Experimental Manuals FPGA for Beginners FPGA Products

FPGA evb – $59 – Cyclone 10 with User Experimental Manual

FII-PRA006/010 User Experimental Manual Product Only $59 Product URL: PRA006 – https://fraserinnovations.com/product/altera-fpga-study-board/ PRA010 – https://fraserinnovations.com/product/fpga-study-board-verilog-and-vhdl-for-beginner-cyclone-10-fpga-development-board-with-jtag-embeded-fii-pra010/ Official Shopping Website: https://fpgamarketing.com/FPGA-Study-Board-Verilog-for-beginner-Cyclone-10-FII-PRA006-FII-PRA006.htm We will send you official newest experimental manuals pdf file, hardware reference guide pdf file, project file zip file, Schematic Diagram pdf file when you order from above links: The advantage of FPGA evb – Cyclone 10 development board: Beginner FPGA study board, cheaper but fully functional. cellphone sized. ( < 100 USD ) power supply and download at the same time, no extra power supply and no extra data transfer…

Experimental Manuals FPGA Tutor Risc-V

AD,DA Experiment , write the data into PCF8591, Read the value of AD acquisition from PCF8591, – FII-PRA040 FPGA Board Experimental 12 – Altera Risc-V FPGA Tutorial :

AD acquisition from PCF8591, AD Experiment, Chip PCF8591, DA Experiment, PCF8591, Photoresist test phenomenon, photoresistor, potentiometer, Potentiometer experiment phenomenon, segment display, the theory of AD conversion, thermistor, Thermistor experiment phenomenon

Experiment 12 AD,DA Experiment 12.1 Experiment Objective Since in the real world, all naturally occurring signals are analog signals, and all that are read and processed in actual engineering are digital signals. There is a process of mutual conversion between natural and industrial signals (digital-to-analog conversion: DAC, analog-to-digital conversion: ADC). The purpose of this experiment is as follows: Learn about the theory of AD conversion Review the knowledge of the IIC protocol learned in the previous experiment and write the data into PCF8591 on the development board. Read the value…

Experimental Manuals FPGA Tutor Risc-V

Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol, reading and writing EEPROM – Altera Risc-V IIC Protocol Transmission FPGA Tutorial – FII-PRA040 FPGA Board Experimental 11

Experiment 11 IIC Protocol Transmission 11.1 Experiment Objective Learning the basic principles of asynchronous IIC bus, and the IIC communication protocol Master the method of reading and writing EEPROM Joint debugging using logic analyzer 11.2 Experiment Implement Correctly write a number to any address in the EEPROM (this experiment writes to the register of 8’h03 address) through the FPGA (here changes the written 8-bit data value by (SW7~SW0)). After writing in successfully, read the data as well. The read data is displayed directly on the segment display. Download the program…

Experimental Manuals FPGA Tutor Risc-V

Asynchronous serial port communication, handshake mechanism, data frame, Asynchronous Serial Port Design and Experiment – FII-PRA040 Risc-V FPGA Board Experimental 10

Asynchronous serial port communication, Asynchronous Serial Port Design, data frame, FIFO, handshake mechanism, SSCOM, teraterm

Experiment 10 Asynchronous Serial Port Design and Experiment 10.1 Experiment Objective Because asynchronous serial ports are very common in industrial control, communication, and software debugging, they are also vital in FPGA development. the basic principles of asynchronous serial port communication, handshake mechanism, data frame Master asynchronous sampling techniques Review the frame structure of the data packet Learning FIFO Joint debugging with common debugging software of PC (SSCOM, teraterm, etc.) 10.2 Experiment Implement Design and transmit full-duplex asynchronous communication interface Tx, Rx Baud rate of 11520 bps, 8-bit data, 1 start…

Experimental Manuals FPGA Tutor Risc-V

Altera Risc-V FPGA Tutorial : Use Dual-port RAM to Read and Write Frame Data – FII-PRA040 FPGA Board Experimental 9

Experiment 9 Use Dual-port RAM to Read and Write Frame Data 9.1 Experiment Objective Learn to configure and use dual-port RAM Learn to use synchronous clock to control the synchronization of frame structure Learn to use asynchronous clock to control the synchronization of frame structure Experiment Implement Observing the synchronization structure of synchronous clock frames using SignalTap II Extended the use of dual-port RAM Design the use of three-stage state machine Design a 16-bit data frame Data is generated by an 8-bit counter: Data={~counta,counta} The ID of the data frame…